Rainbow-electronics ATR0625 Manuel d'utilisateur

Naviguer en ligne ou télécharger Manuel d'utilisateur pour Récepteur GPS Rainbow-electronics ATR0625. Rainbow Electronics ATR0625 User Manual Manuel d'utilisatio

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Features
16-channel GPS Correlator
8192 Search Bins with GPS Acquisition Accelerator
Accuracy: 2.5m CEP (Stand-Alone, S/A off)
Time to First Fix: 34s (Cold Start)
Acquisition Sensitivity: –142 dBm
Tracking Sensitivity: –158 dBm
Utilizes the ARM7TDMI
®
ARM
®
Thumb
®
Processor Core
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Embedded ICE (In-circuit Emulator)
128 Kbyte Internal RAM
384 Kbyte Internal ROM with u-blox GPS Firmware
6-channel Peripheral Data Controller (PDC)
8-level Priority, Individually Maskable, Vectored Interrupt Controller
2 External Interrupts
24 User-programmable I/O Lines
1 USB Device Port
Universal Serial Bus (USB) V2.0 Full-speed Device
Embedded USB V2.0 Full-speed Transceiver
Suspend/Resume Logic
Ping-pong Mode for Isochronous and Bulk Endpoints
2 USARTs
2 Dedicated Peripheral Data Controller (PDC) Channels per USART
Master/Slave SPI Interface
2 Dedicated Peripheral Data Controller (PDC) Channels
8-bit to 16-bit Programmable Data Length
4 External Slave Chip Selects
Programmable Watchdog Timer
Advanced Power Management Controller (APMC)
Peripherals Can Be Deactivated Individually
Geared Master Clock to Reduce Power Consumption
Sleep State with Disabled Master Clock
Hibernate State with 32.768 kHz Master Clock
Real Time Clock (RTC)
2.3V to 3.6V or 1.8V Core Supply Voltage
Includes Power Supervisor
1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance
4 Kbytes Battery Backup Memory
8 mm × 8 mm 56 Pin QFN56 Package
Pb-free, RoHS-compliant, Green
GPS Baseband
Processor
SuperSense
ATR0625
Preliminary
Rev. 4925A–GPS–02/06
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Résumé du contenu

Page 1 - Preliminary

Features• 16-channel GPS Correlator– 8192 Search Bins with GPS Acquisition Accelerator– Accuracy: 2.5m CEP (Stand-Alone, S/A off)– Time to First Fix:

Page 2

104925A–GPS–02/06ATR0625 [Preliminary] 3.3.2 Sensitivity Settings3.3.3 Serial I/O ConfigurationThe ATR0625 features a two-stage I/O message and prot

Page 3

114925A–GPS–02/06 ATR0625 [Preliminary] The following message settings are used in the tables below:The following settings apply if GPSMODE configura

Page 4

124925A–GPS–02/06ATR0625 [Preliminary] 3.3.4 USB Power ModeFor correct response to the USB host queries, the device has to know its power mode. This

Page 5

134925A–GPS–02/06 ATR0625 [Preliminary] The Antenna Supervisor Software will be configured as follows:1. Enable Control Signal2. Enable Short Circuit

Page 6

144925A–GPS–02/06ATR0625 [Preliminary] 3.4 External Connections for a Working GPS SystemFigure 3-2. Example of an External Connection ATR0601ATR0625

Page 7

154925A–GPS–02/06 ATR0625 [Preliminary] Table 3-15. Recommended Pin Connection Pin Name Recommended External CircuitP0/NANTSHORTInternal pull-down re

Page 8

164925A–GPS–02/06ATR0625 [Preliminary] 3.4.1 Connecting an Optional Serial EEPROMThe ATR0625 offers the possibility to connect an external serial EE

Page 9

174925A–GPS–02/06 ATR0625 [Preliminary] 4. Power SupplyThe baseband IC is supplied with four distinct supply voltages:• VDD18, the nominal 1.8V suppl

Page 10 - ATR0625 [Preliminary]

184925A–GPS–02/06ATR0625 [Preliminary] The baseband IC contains a built in low dropout voltage regulator LDO18. This regulator can be used if the ho

Page 11 - ATR0625 [Preliminary]

194925A–GPS–02/06 ATR0625 [Preliminary] The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected t

Page 12

24925A–GPS–02/06ATR0625 [Preliminary] 1. DescriptionThe GPS baseband processor ATR0625 includes a 16-channel GPS correlator and is based on the ARM7

Page 13

204925A–GPS–02/06ATR0625 [Preliminary] 5. OscillatorFigure 5-1. Crystal Connection XT_INXT_OUTRTCATR0625 internal32 kHzCrystalOscillator32.768 kHz c

Page 14

214925A–GPS–02/06 ATR0625 [Preliminary] 7. Electrical Characteristics If no additional information is given in column Test Conditions, the values app

Page 15

224925A–GPS–02/06ATR0625 [Preliminary] 1.23Input-leakage Current (standard Inputs and I/Os)VDD18 = 1.95V VIL = 0VILEAK–1 +1 µA1.24 Input Capacitance

Page 16

234925A–GPS–02/06 ATR0625 [Preliminary] 9. ESD SensitivityThe ATR0625 is an ESD sensitive device. The current ESD values are to be defined.Observe pr

Page 17

244925A–GPS–02/06ATR0625 [Preliminary] 11. LDOBAT and Backup DomainThe LDOBAT is a built in low dropout voltage regulator which provides the supply

Page 18

254925A–GPS–02/06 ATR0625 [Preliminary] 13. Package QFN56 12. Ordering InformationExtended Type Number Package MPQ RemarksATR0625-PYQW QFN56 20008 mm

Page 19

Printed on recycled paper.4925A–GPS–02/06© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® an

Page 20

34925A–GPS–02/06 ATR0625 [Preliminary] Figure 1-1. ATR0625 Block Diagram NSLEEPNSHDNXT_INNRESETTMSTCKTDOTDINTRSTDBG_ENCLK23RF_ONP0/NANTSHORTP15/ANTON

Page 21

44925A–GPS–02/06ATR0625 [Preliminary] 2. Architectural Overview2.1 DescriptionThe ATR0625 architecture consists of two main buses, the Advanced Syst

Page 22

54925A–GPS–02/06 ATR0625 [Preliminary] 3. Pin Configuration3.1 PinoutFigure 3-1. Pinout QFN56 (Top View) 42 2911443 2856 15ATR0625Table 3-1. ATR0625

Page 23

64925A–GPS–02/06ATR0625 [Preliminary] P14 1 I/O Configurable (PD) NAADET1 “0”P15 17 I/O PD ANTONP16 6 I/O Configurable (PU) NEEPROM SIGHI1 NWD_OVFP1

Page 24

74925A–GPS–02/06 ATR0625 [Preliminary] 3.2 Signal DescriptionTable 3-2. ATR0625 Signal Description Module Name Function Type Active Level CommentEBI

Page 25

84925A–GPS–02/06ATR0625 [Preliminary] JTAG/ICETMS Test Mode Select Input – Internal pull-up resistorTDI Test Data In Input – Internal pull-up resist

Page 26 - Regional Headquarters

94925A–GPS–02/06 ATR0625 [Preliminary] 3.3 Setting GPSMODE0 to GPSMODE12The start-up configuration of a ROM-based system without external non-volatil

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