Rainbow-electronics ISD5100 Manuel d'utilisateur

PRELIMINARY Publication Release Date: October, 2003 - 1 - Revision 0.2 ISD5100 SERIES SINGLE-CHIP 1 TO 16 MINUTES DURATION VOICE RECORD/

ISD5100 – SERIES - 10 - interface. These are the RAC timing pin and the INT pin for interrupts to the controller. Communications with all the inter

ISD5100 – SERIES Publication Release Date: October, 2003 - 11 - Revision 0.2 operation, voice from Mic inputs are fed to AUX OUT and transmitted

ISD5100 – SERIES - 12 - Digital data is sent and received serially over the I2C interface. The data is serial-to-parallel converted and stored in on

ISD5100 – SERIES Publication Release Date: October, 2003 - 13 - Revision 0.2 Pinout Table A1 A0 Slave Address R/W Bit HEX Value0 0 <100 0

ISD5100 – SERIES - 14 - Note that the processor could have sent an I2C STOP after the Status Word data transfer and aborted the transfer of the Addre

ISD5100 – SERIES Publication Release Date: October, 2003 - 15 - Revision 0.2 7.3.1.2. Load Command Byte Register (Single Byte Load): A single by

ISD5100 – SERIES - 16 - 7.3.2. I2C Control Registers The ISD5100 Series are controlled by loading commands to, or, reading from, the internal command

ISD5100 – SERIES Publication Release Date: October, 2003 - 17 - Revision 0.2 Register Bits The register load may be used to modify a command se

ISD5100 – SERIES - 18 - OPCODE COMMAND BYTE TABLE Pwr Function Bits Register Bits OPCODE HEX PU DAB FN2 FN1 FN0 RG2 RG1 RG0 COMMAND BIT NUMBER

ISD5100 – SERIES Publication Release Date: October, 2003 - 19 - Revision 0.2 7.3.4. Data Bytes In the I2C write mode, the device can accept data

ISD5100 – SERIES - 2 - 1. GENERAL DESCRIPTION The ISD5100 ChipCorder Series provide high quality, fully integrated, single-chip Record/Playback solu

ISD5100 – SERIES - 20 - 7.3.5. Configuration Resiter Bytes The configuration register bytes are defined, in detail, in the drawings of section 7.4 on

ISD5100 – SERIES Publication Release Date: October, 2003 - 21 - Revision 0.2 AGC AMP Power DownFilter Power Down SAMPLE RATE (& Filter) Set

ISD5100 – SERIES - 22 - Record Mode The command sequence for an Analog Record would be a four byte sequence consisting of the Slave Address (80h), th

ISD5100 – SERIES Publication Release Date: October, 2003 - 23 - Revision 0.2 To select this mode, the following control bits must be configured

ISD5100 – SERIES - 24 - 6. Don’t Care bits—The following stages are not used in Feed Through Mode. Their bits may be set to either level. In this ex

ISD5100 – SERIES Publication Release Date: October, 2003 - 25 - Revision 0.2 4. Power up the LOW PASS FILTER—Bit FLPD controls the power up sta

ISD5100 – SERIES - 26 - 5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS FILTER stage. This is bit D1 of CFG1 an

ISD5100 – SERIES Publication Release Date: October, 2003 - 27 - Revision 0.2 6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-u

ISD5100 – SERIES - 28 - 7.4. ANALOG MODE 7.4.1. Aux In and Ana In Description The AUX IN is an additional audio input to the ISD5100-Series, such as

ISD5100 – SERIES Publication Release Date: October, 2003 - 29 - Revision 0.2 7.4.2. ISD5100 Series Analog Structure (left half) Description IN

ISD5100 – SERIES Publication Release Date: October, 2003 - 3 - Revision 0.2 2. FEATURES Fully-Integrated Solution • Single-chip voice record/pl

ISD5100 – SERIES - 30 - 7.4.3. ISD5100 Series Aanalog Structure (right half) Description SUM1SU M2Σ2 (S2M 1,S2 M0)FI LTE RMU XSUM2 SUMMINGAMPARRAY2

ISD5100 – SERIES Publication Release Date: October, 2003 - 31 - Revision 0.2 7.4.4. Volume Control Description VO LSU M2VOLMUXSU M1IN P2 AN A I

ISD5100 – SERIES - 32 - 7.4.5. Speaker and Aux Out Description Sp eak erSP+SP–AUX OUTCar Kit(1 Vp-p Max)ANA IN AMPOUTPUTMU XFILTOSU M 22 VOL(OPS1,O

ISD5100 – SERIES Publication Release Date: October, 2003 - 33 - Revision 0.2 7.4.6. Ana Out Description Chip SetAN A OU T +AN A OU T –*VOL*F

ISD5100 – SERIES - 34 - MI C+MI C–ACAPFTHRUAGC1 ( AG PD)6 dBTo AutoMute(Playback Only)** Differential PathAGC 1514131211109876543210VLS1 VLS0 VOL2 VO

ISD5100 – SERIES Publication Release Date: October, 2003 - 35 - Revision 0.2 1. Gain from ANA IN to SP+/- 2. Gain from ANA IN to ARRAY IN 3.

ISD5100 – SERIES - 36 - 7.5. DIGITAL MODE 7.5.1. Erasing Digital Data The Digital Erase command can only erase an entire page at a time. This means t

ISD5100 – SERIES Publication Release Date: October, 2003 - 37 - Revision 0.2 7.5.3. Reading Digital Data The Digital Read command utilizes the c

ISD5100 – SERIES - 38 - WaitACK WaitSCLHigh SendByte(row%256) - low address byte WaitACK WaitSCLHigh I2CStop repeat until the number of RAC pulse

ISD5100 – SERIES Publication Release Date: October, 2003 - 39 - Revision 0.2 WaitSCLHigh SendByte(0x40) - Exit Digital Mode Command WaitACK

ISD5100 – SERIES - 4 - 3. BLOCK DIAGRAM ISD5100-Series Block Diagram AUX IN AMP 1.0 / 1.4 / 2.0 / 2.8 AGC SUM1 MUXVol MUXFilterMUXLow PassFilterSU

ISD5100 – SERIES - 40 - S SLAVE ADDRESSAW 40hAPS SLAVE ADDRESSAW CONAPASSLAVE ADDRESS W Command ByteD1ADATAADATAAHigh Addr. Byte Lo

ISD5100 – SERIES Publication Release Date: October, 2003 - 41 - Revision 0.2 SUGGESTED FLOW FOR DIGITAL ERASE INISD5100-SeriesENTER DIGITALMODES

ISD5100 – SERIES - 42 - 7.5.4.2. Write Digital Data Write ===== I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendB

ISD5100 – SERIES Publication Release Date: October, 2003 - 43 - Revision 0.2 I2CStart SendByte(0x80) - Write, Slave address zero WaitACK W

ISD5100 – SERIES - 44 - SUGGESTED FLOW FOR DIGITAL WRITE IN ISD5100-SeriesENTER DIGITALMODESEND W RITECOMMAND W/START ADDRESSEXIT DIGITALMODEDEVICEP

ISD5100 – SERIES Publication Release Date: October, 2003 - 45 - Revision 0.2 7.5.4.3. Read Digital Data Read ===== I2CStart SendByte(0x80)

ISD5100 – SERIES - 46 - } I2CStop() I2CStart SendByte(0x80) - Write, Slave address zero WaitACK WaitSCLHigh SendByte(0x40) - Exit Digita

ISD5100 – SERIES Publication Release Date: October, 2003 - 47 - Revision 0.2 SUGGESTED FLOW FOR DIGITAL READ IN ISD5100-SeriesENTER DIGITALMODE

ISD5100 – SERIES - 48 - 7.6. PIN DETAILS 7.6.1. Digital I/O Pins SCL (Serial Clock Line) The Serial Clock Line is a bi-directional clock line. I

ISD5100 – SERIES Publication Release Date: October, 2003 - 49 - Revision 0.2 RAC Waveform During Digital Erase @ 8kHz Operation 1.25 msTRACE.25

ISD5100 – SERIES Publication Release Date: October, 2003 - 5 - Revision 0.2 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION...

ISD5100 – SERIES - 50 - A0, A1 (Address Pins) These two pins are normally strapped for the desired address that the ISD5100 Series will have on the

ISD5100 – SERIES Publication Release Date: October, 2003 - 51 - Revision 0.2 ACAP (AGC Capacitor) This pin provides the capacitor connection for

ISD5100 – SERIES - 52 - ANA IN (Analog Input) The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the I2C interfac

ISD5100 – SERIES Publication Release Date: October, 2003 - 53 - Revision 0.2 AUX IN (Auxiliary Input) The AUX IN is an additional audio input to

ISD5100 – SERIES - 54 - 7.6.3. Power and Ground Pins VCCA, VCCD (Voltage Inputs) To minimize noise, the analog and digital circuits in the ISD5100 Se

ISD5100 – SERIES Publication Release Date: October, 2003 - 55 - Revision 0.2 7.6.4. PCB Layout Examples For SOIC package : PC board traces an

ISD5100 – SERIES - 56 - 8.TIMING DIAGRAMS 8.1. I2C TIMING DIAGRAM t LOWtSCLKtHIGHtftrt SU-DAT tSU-STO t f START SDA SCL STOP

ISD5100 – SERIES Publication Release Date: October, 2003 - 57 - Revision 0.2 I2C INTERFACE TIMING STANDARD-MODE FAST-MODE PARAMETER SYMBOL

ISD5100 – SERIES - 58 - 8.2. PLAYBACK AND STOP CYCLE SDASCLANA INANA OUTDATA CLOCK PULSESSTOPPLAY AT ADDRtSTOPtSTARTSTOP

ISD5100 – SERIES Publication Release Date: October, 2003 - 59 - Revision 0.2 8.3. EXAMPLE OF POWER UP COMMAND (FIRST 12 BITS)

ISD5100 – SERIES - 6 - 7.4.6. Ana Out Description ...

ISD5100 – SERIES - 60 - 9. ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)(1) Condition Value Junction temperature 1500C Storage

ISD5100 – SERIES Publication Release Date: October, 2003 - 61 - Revision 0.2 OPERATING CONDITIONS (PACKAGED PARTS) Condition Value Commercial o

ISD5100 – SERIES - 62 - 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS Symbol Parameters Min(2) Typ(1)Max(2) Units Conditions VIL Input

ISD5100 – SERIES Publication Release Date: October, 2003 - 63 - Revision 0.2 10.2. TIMING PARAMETERS Symbol Parameters Min(2) Typ(1) Max(2)

ISD5100 – SERIES - 64 - 4.0 kHz (sample rate) 512 msec (9) TRACL RAC Clock Low Time 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample r

ISD5100 – SERIES Publication Release Date: October, 2003 - 65 - Revision 0.2 10.3. ANALOG PARAMETERS MICROPHONE INPUT(14) Symbol Parameters Mi

ISD5100 – SERIES - 66 - AUX IN(14) Symbol Parameters Min(2) Typ(1)(14) Max(2) Units Conditions VAUX IN AUX IN Input Voltage 1.0 V Peak-to-

ISD5100 – SERIES Publication Release Date: October, 2003 - 67 - Revision 0.2 VCC and VCC pins FR Frequency Response (300-3400 Hz) +0.5 dB W

ISD5100 – SERIES - 68 - CRTANA OUT/AUX OUT ANA OUT to AUX OUT Cross Talk -65 dB 1 kHz 0TLP output from ANA OUT, with ANA IN AC coupled to VSSA,

ISD5100 – SERIES Publication Release Date: October, 2003 - 69 - Revision 0.2 Conditions 1. Typical values: TA = 25°C and Vcc = 3.0V. 2. All mi

ISD5100 – SERIES Publication Release Date: October, 2003 - 7 - Revision 0.2 5. PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 101112131428 27 26 25

ISD5100 – SERIES - 70 - Start and stop conditions Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW

ISD5100 – SERIES Publication Release Date: October, 2003 - 71 - Revision 0.2 Acknowledge The number of data bytes transferred between t

ISD5100 – SERIES - 72 - 10.5. I2C PROTOCOL Since the I2C protocol allows multiple devices on the bus, each device must have an address. This address

ISD5100 – SERIES Publication Release Date: October, 2003 - 73 - Revision 0.2 Master Reads from Slave immediately after first byte (Read Mode) R

ISD5100 – SERIES - 74 - 11. TYPICAL APPLICATION CIRCUIT SCLSDAA1A0MIC+MIC-ACAPRACINTVCCDVCCDVCCAVSSDVSSDVSSAVSSAVSSASP+SP-51XX1234810132425272817569

ISD5100 – SERIES Publication Release Date: October, 2003 - 75 - Revision 0.2 12. PACKAGE SPECIFICATION 12.1. 28-LEAD 8X13.4MM PLASTIC THIN SMALL

ISD5100 – SERIES - 76 - 12.2. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 2827262524232221 20 19 18 17161512345 6789101112 1314A

ISD5100 – SERIES Publication Release Date: October, 2003 - 77 - Revision 0.2 12.3. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP) Plast

ISD5100 – SERIES - 78 - 12.4 ISD5116 DIE INFORMATION ≈ISD5116≈VSSAMIC +MIC -ANA OUT +ANA OUT -ACAPSP -VSSA [2]SP +VCCA [2]ANA INAUX INAUX OUTVSSDVS

ISD5100 – SERIES Publication Release Date: October, 2003 - 79 - Revision 0.2 ISD5116 Pad Coordinates (with respect to die center in µm) Pad

ISD5100 – SERIES - 8 - 6. PIN DESCRIPTION Pin Name SOIC/PDIP TSOP Functionality SCL 1 8 I2C Serial Clock Line: to clock the data into and out of t

ISD5100 – SERIES - 80 - 12.5 ISD5108 DIE INFORMATION ≈ISD5108≈VSSAMIC +MIC -ANA OUT +ANA OUT -ACAPSP -VSSA [2]SP +VCCA [2]ANA INAUX INAUX OUTVSSDVS

ISD5100 – SERIES Publication Release Date: October, 2003 - 81 - Revision 0.2 ISD5108 Pad Coordinates (with respect to die center in µm) Pad P

ISD5100 – SERIES - 82 - 12.6 ISD5104 DIE INFORMATION ≈ISD5104≈VSSAMIC +MIC -ANA OUT +ANA OUT -ACAPSP -VSSA [2]SP +VCCA [2]ANA INAUX INAUX OUTVSSDVS

ISD5100 – SERIES Publication Release Date: October, 2003 - 83 - Revision 0.2 ISD5104 Pad Coordinates (with respect to die center in µm) Pad

ISD5100 – SERIES - 84 - 12.7 ISD5102 DIE INFORMATION ≈ISD5102≈VSSAMIC +MIC -ANA OUT +ANA OUT -ACAPSP -VSSA [2]SP +VCCA [2]ANA INAUX INAUX OUTVSSDVS

ISD5100 – SERIES Publication Release Date: October, 2003 - 85 - Revision 0.2 ISD5102 Pad Coordinates (with respect to die center in µm) Pad

ISD5100 – SERIES - 86 - 13. ORDERING INFORMATION Winbond Part Number Description When ordering ISD5100 Series devices, please re

ISD5100 – SERIES Publication Release Date: October, 2003 - 87 - Revision 0.2 14. VERSION HISTORY VERSION DATE DESCRIPTION 0.1 Mar 2003 New da

ISD5100 – SERIES - 88 - Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) L

ISD5100 – SERIES Publication Release Date: October, 2003 - 9 - Revision 0.2 7. FUNCTIONAL DESCRIPTION 7.1. OVERVIEW 7.1.1 Speech/Voice Quality T