Rainbow-electronics AT24C128 Manuel d'utilisateur

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1
Features
Low-voltage and Standard-voltage Operation
–2.7(V
CC
=2.7Vto5.5V)
–1.8(V
CC
=1.8Vto3.6V)
Internally Organized 16,384 x 8 and 32,768 x 8
2-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
64-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Typical)
High Reliability
Endurance: 100,000 Write Cycles
Data Retention: 40 Years
Automotive Grade and Extended Temperature Devices Available
8-pin JEDEC PDIP, 8-pin JEDEC and EIAJ SOIC, 8-pin TSSOP, 14-pin TSSOP and 8-ball
dBGA
TM
Packages
Description
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The devices are
available in space-saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, 8-
pin TSSOP, 14-pin TSSOP and 8-ball dBGA packages. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.
2-wire Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT24C128
AT24C256
Rev. 0670H–SEEPR–07/02
Pin Configurations
Pin Name Function
A0 - A1 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
8-pin PDIP
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
8-pin SOIC
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
14-pin TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A0
A1
NC
NC
NC
NC
GND
VCC
WP
NC
NC
NC
SCL
SDA
8-ball dBGA
Bottom View
VCC
WP
SCL
SDA
A0
A1
NC
GND
1
2
3
4
8
7
6
5
8-pin TSSOP
1
2
3
4
8
7
6
5
A0
A1
NC
GND
VCC
WP
SCL
SDA
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Résumé du contenu

Page 1 - AT24C256

1Features• Low-voltage and Standard-voltage Operation–2.7(VCC=2.7Vto5.5V)–1.8(VCC=1.8Vto3.6V)• Internally Organized 16,384 x 8 and 32,768 x 8• 2-wire

Page 2

10AT24C128/2560670H–SEEPR–07/02ReadOperationsRead operations are initiated the same way as write operations with the exception that theread/write sele

Page 3

11AT24C128/2560670H–SEEPR–07/02Figure 3. Page WriteNotes: (* = DON’TCAREbit)(† =DON’T CARE bit for the 128K)Figure 4. Current Address ReadFigure 5. Ra

Page 4

12AT24C128/2560670H–SEEPR–07/02Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characterist

Page 5

13AT24C128/2560670H–SEEPR–07/02Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characterist

Page 6

14AT24C128/2560670H–SEEPR–07/02Packaging Information8P3 – PDIP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8P3, 8-lead, 0.300" W

Page 7

15AT24C128/2560670H–SEEPR–07/028S1 – JEDEC SOIC 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. Note:10/10/018S1, 8-lead (0.150"

Page 8

16AT24C128/2560670H–SEEPR–07/028S2 – EIAJ SOIC2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8S2, 8-lead, 0.209" Body, Plastic Sma

Page 9

17AT24C128/2560670H–SEEPR–07/028U1 – dBGA2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8U1, 8-ball 0.75 pitch, Die Ball Grid ArrayPack

Page 10 - AT24C128/256

18AT24C128/2560670H–SEEPR–07/028U6 – dBGA2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8U6, 8-ball 0.75 pitch, Die Ball Grid ArrayPack

Page 11

19AT24C128/2560670H–SEEPR–07/028A2 – TSSOP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 5/30/02COMMON DIMENSIONS(Unit of Measure = mm)

Page 12

2AT24C128/2560670H–SEEPR–07/02Block DiagramAbsolute Maximum Ratings*Operating Temperature ... -55°Cto+125°C*NOTICE: Str

Page 13

20AT24C128/2560670H–SEEPR–07/0214A2–TSSOP2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 12/28/0114A2,14-lead (4.4 x 5 mm Body), 0.65 Pi

Page 14

Printed on recycled paper.0670H–SEEPR–07/02 xM© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than tho

Page 15

3AT24C128/2560670H–SEEPR–07/02Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into eachEEPROM device and negativ

Page 16

4AT24C128/2560670H–SEEPR–07/02Pin Capacitance(1)Note: 1. This parameter is characterized and is not 100% tested.DC Characteristics(1)Note: 1. VILmin a

Page 17

5AT24C128/2560670H–SEEPR–07/02AC CharacteristicsNotes: 1. This parameter is characterized and is not 100% tested.2. AC measurement conditions:RL(conne

Page 18

6AT24C128/2560670H–SEEPR–07/02DeviceOperationCLOCK and DATA TRANSITIONS: TheSDApinisnormallypulledhighwithanexternaldevice. Data on the SDA pin may ch

Page 19

7AT24C128/2560670H–SEEPR–07/02Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note: 1.

Page 20

8AT24C128/2560670H–SEEPR–07/02Data ValidityStart and Stop DefinitionOutput Acknowledge

Page 21 - 0670H–SEEPR–07/02 xM

9AT24C128/2560670H–SEEPR–07/02DeviceAddressingThe 128K/256K EEPROM requires an 8-bit device address word following a start condition toenable the chip

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