1Features• Single 2.5V - 3.6V or 2.7V - 3.6V Supply• Serial Peripheral Interface (SPI) Compatible• 20 MHz Max Clock Frequency• Page Program Operation–
10AT45DB081B2225D–DFLSH–10/02Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock
11AT45DB081B2225D–DFLSH–10/02Note: r = Reserved BitP = Page Address BitB = Byte/Buffer Address Bitx = Don’t CareTable 4. Detailed Bit-level Addressin
12AT45DB081B2225D–DFLSH–10/02Note: 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before
13AT45DB081B2225D–DFLSH–10/02AC CharacteristicsSymbol ParameterAT45DB081B(2.5V Version) AT45DB081BUnitsMin Max Min MaxfSCKSCK Frequency 15 20 MHzfCARS
14AT45DB081B2225D–DFLSH–10/02Input Test Waveforms and Measurement LevelstR, tF < 3 ns (10% to 90%)Output Test LoadAC WaveformsTwo different timing
15AT45DB081B2225D–DFLSH–10/02Reset Timing (Inactive Clock Polarity Low Shown)Note: The CS signal should be in the high state before the RESET signal i
16AT45DB081B2225D–DFLSH–10/02Write Operations The following block diagram and waveforms illustrate the various write sequencesavailable.Main Memory Pa
17AT45DB081B2225D–DFLSH–10/02Read Operations The following block diagram and waveforms illustrate the various read sequencesavailable.Main Memory Page
18AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity LowContinuous Array Read (Opcode: 68H)Main Memory Page Read (Opc
19AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)Buffer Read (Opcode: 54H or 56H)Status Register R
2AT45DB081B2225D–DFLSH–10/02stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three step Read-Modify-Write o
20AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity HighContinuous Array Read (Opcode: 68H)Main Memory Page Read (Op
21AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)Buffer Read (Opcode: 54H or 56H)Status Register
22AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 0Continuous Array Read (Opcode: E8H)Main Memory Page Read (Opcode: D2H)SI11XXXC
23AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 0 Buffer Read (Opcode: D4H or D6H)Status Register Read (Opcode: D7H)SI11010XXXC
24AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 3Continuous Array Read (Opcode: E8H)Main Memory Page Read (Opcode: D2H)SI11XXXC
25AT45DB081B2225D–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 3 (Continued)Buffer Read (Opcode: D4H or D6H)Status Register Read (Opcode: D7H)
26AT45DB081B2225D–DFLSH–10/02Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire ArrayNotes: 1. This type of algorithm is us
27AT45DB081B2225D–DFLSH–10/02Figure 2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of a DataFlash sector mus
28AT45DB081B2225D–DFLSH–10/02Ordering InformationfSCK (MHz)ICC (mA)Ordering Code Package Operation RangeActive Standby20 10 0.01 AT45DB081B-CCAT45DB08
29AT45DB081B2225D–DFLSH–10/02Packaging Information14C1 – CBGA 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 14C1, 14-ball (3 x 5 Ar
3AT45DB081B2225D–DFLSH–10/02Memory Architecture DiagramDevice Operation The device operation is controlled by instructions from the host processor. Th
30AT45DB081B2225D–DFLSH–10/0228R – SOICPIN 10º ~ 8º 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 28R, 28-lead, 0.330" Body Wi
31AT45DB081B2225D–DFLSH–10/0228T – TSOP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small
Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai
4AT45DB081B2225D–DFLSH–10/02cycle, allowing one continuous read operation without the need of additional addresssequences. To perform a continuous rea
5AT45DB081B2225D–DFLSH–10/02loaded into the device. After the last bit of the opcode is shifted in, the eight bits of thestatus register, starting wit
6AT45DB081B2225D–DFLSH–10/02BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: Apreviously erased page within main memory can be programmed wi
7AT45DB081B2225D–DFLSH–10/02MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-tion of the Buffer Write and Buffer to Main Memory Pa
8AT45DB081B2225D–DFLSH–10/02If a sector is programmed or reprogrammed sequentially page-by-page, then the pro-gramming algorithm shown in Figure 1 on
9AT45DB081B2225D–DFLSH–10/02WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memorycannot be reprogrammed. The only way to re
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