Rainbow-electronics DAB-IMU-C01 Manuel d'utilisateur télécharger pdf (Page 5)

ADIS16250/ADIS16255

Rev. B | Page 5 of 20

TIMING SPECIFICATIONS

= −40°C to +85°C, V

= 5.0 V, unless otherwise noted.

Table 2.

Parameter Description Min

Typ Max

Unit

SCLK

Fast mode, SMPL_PRD ≤ 0x07 (f

≥ 64 Hz) 0.01 2.5 MHz

Normal mode, SMPL_PRD ≥ 0x08 (f

≤ 56.9 Hz) 0.01 1.0 MHz

DATARATE

Data rate period, fast mode, SMPL_PRD ≤ 0x07 (f

≥ 64 Hz) 32 s

Data rate period, normal mode, SMPL_PRD ≥ 0x08 (f

≤ 56.9 Hz) 42 s

STALL

Stall period, fast mode, SMPL_PRD ≤ 0x07 (f

≥ 64 Hz) 9 s

Stall period, normal mode, SMPL_PRD ≥ 0x08 (f

≤ 56.9 Hz) 12 s

Chip select to clock edge 48.8 ns

DAV

Data output valid after SCLK falling edge

100 ns

DSU

Data input setup time before SCLK rising edge 24.4 ns

DHD

Data input hold time after SCLK rising edge 48.8 ns

Data output fall time 5 12.5 ns

Data output rise time 5 12.5 ns

SFS

CS high after SCLK edge

5 ns

Flash update time (power supply must be within range) 50 ms

Guaranteed by design; not production tested.

The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of

. The rest of the DOUT bits are clocked after the falling edge of SCLK and

are governed by this specification.

This parameter may need to be expanded to allow for proper capture of the LSB. After

goes high, the DOUT line goes into a high impedance state.

SCLK

DATARATE

DATASTALL

06070-026

Figure 2. SPI Chip Select Timing

SCLK

DOUT

DIN

1 2 3 4 5 6 15 16

W/R A5 A4 A3 A2

MSB DB14

D1 LSB

DB13 DB12 DB10DB11 DB2 LSBDB1

SFS

DAV

DHD

DSU

*NOT DEFINED

06070-003

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)

1 2 3 4 5 6 7 8 9 10 ... 19 20

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Rainbow-electronics DAB-IMU-C01 Manuel d'utilisateur Page 5

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