Rainbow-electronics DS1267 Manuel d'utilisateur

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1 of 12 102199
VB
NC
H1
L1
W1
RST
CLK
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
CC
NC
S
OUT
W0
H0
L0
C
OUT
DQ
16-Pin SOIC (300-mil)
See Mech. Drawings Section
FEATURES
Ultra-low power consumption, quiet,
pumpless design
Two digitally controlled, 256-position
potentiometers
Serial port provides means for setting and
reading both potentiometers
Resistors can be connected in series to
provide increased total resistance
14-pin DIP, 16-pin SOIC, 20-pin TSSOP
packages
Resistive elements are temperature
compensated to ±0.3 LSB relative linearity
Standard resistance values:
DS1267-10 ~ 10 k
DS1267-50 ~ 50 k
DS1267-100 ~ 100 k
Operating Temperature Range:
Industrial: -40°C to +85°C
PIN ASSIGNMENT
PIN DESCRIPTIONS
L0, L1 - Low End of Resistor
H0, H1 - High End of Resistor
W0, W1 - Wiper Terminal of Resistor
V
B
- Substrate Bias Voltage
S
OUT
- Stacked Configuration Output
RST - Serial Port Reset Input
DQ - Serial Port Data Input
CLK - Serial Port Clock Input
C
OUT
- Cascade Port Output
V
CC
- +5 Volt Supply
GND - Ground
NC - No Internal Connection
14-Pin DIP (300-mil)
See Mech. Drawings Section
VB
H1
L1
W1
RST
CLK
GND
14
13
12
11
10
9
8
1
2
3
4
5
6
7
V
CC
S
OUT
W0
H0
L0
C
OUT
DQ
DS1267
Dual Digital Potentiometer Chip
www.dalsemi.com
20-Pin TSSOP (173-mil)
VB
NC
H1
L1
W1
RST
CLK
20
19
18
17
16
15
14
1
2
3
4
5
6
7
V
CC
NC
NC
S
OUT
W0
H0
L0
8
9
10
13
12
11
C
OUT
NC
NCNC
GND
DQ
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Résumé du contenu

Page 1 - PIN DESCRIPTIONS

1 of 12 102199VBNCH1L1W1RSTCLKGND16151413121110912345678VCCNCSOUTW0H0L0COUTDQ16-Pin SOIC (300-mil)See Mech. Drawings SectionFEATURES Ultra-low power

Page 2 - OPERATION

DS126710 of 12 1021994. Relative linearity is used to determine the change in voltage between successive tap positions. Devicetest limits ±0.5 LSB.5.

Page 3 - DS1267 BLOCK DIAGRAM Figure 1

DS126711 of 12 102199(C) END OF COMMUNICATION TRANSACTIONDIGITAL OUTPUT LOAD SCHEMATIC Figure 10

Page 4 - CASCADE OPERATION

DS126712 of 12 102199TYPICAL SUPPLY CURENT VS. SERIAL CLOCK RATE Figure 11

Page 5

DS12672 of 12 102199DESCRIPTIONThe DS1267 Dual Digital Potentiometer Chip consists of two digitally controlled, solid-statepotentiometers. Each potent

Page 6

DS12673 of 12 102199DS1267 BLOCK DIAGRAM Figure 1I/O SHIFT REGISTER Figure 2Transmission of data always begins with the stack select bit followed by t

Page 7 - FIX GAIN ATTENUATOR Figure 8

DS12674 of 12 102199STACKED CONFIGURATIONThe potentiometers of the DS1267 can be connected in series as shown in Figure 3. This is referred to asthe s

Page 8

DS12675 of 12 102199The COUToutput of the DS1267 can be used to drive the DQ input of another DS1267. When connectingmultiple devices, the total numbe

Page 9 - RST Inactive

DS12676 of 12 102199LINEARITY MEASUREMENT CONFIGURATION Figure 5NOTE:In this setup, a ±2% delta in total resistance R0 to R1 would cause a ±2.5 MI err

Page 10 - TIMING DIAGRAMS Figure 9

DS12677 of 12 102199INVERTING VARIABLE GAIN AMPLIFIER Figure 7FIX GAIN ATTENUATOR Figure 8

Page 11 - 11 of 12 102199

DS12678 of 12 102199ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground (VB=GND) -0.1V to +7.0VVoltage on Resistor Pins when VB=-5.5V -5.5V

Page 12 - 12 of 12 102199

DS12679 of 12 102199ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C; VCC = 5.0V ± 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESEnd-to-End Resistor Tole

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