
DS1854
Dual Temperature-Controlled Resistors with
Two Monitors
10 ____________________________________________________________________
ADEN
(ADDRESS
ENABLE)
NO. OF SEPARATE
DEVICE
ADDRESSES
ADDITIONAL
1 (Main Device only)
Table 4. ADEN Address Configuration
ADDRESS
MAIN ADDRESS
00A0h A2h
01A0h
EEPROM
(Table 01, 8Ch)
10N/A A2h
11N/A
EEPROM
(Table 01, 8Ch)
Table 5. ADEN and ADFIX Bits
MAIN
DEVICE
MON LOOK-UP
TABLE CONTROL
R0 LOOK-UP
TABLE
AUXILIARY
DEVICE
0
DEC
0
95
96
127
128
143
199
MEMORY PARTITION WITH ADEN BIT = 0
EN
EN
EN
EN
SEL
EN
SEL
7Fh
5Fh
60h
7Fh
80h
80h
C7h
RESERVED RESERVED
8Fh
TABLE SELECT
MAIN DEVICE ENABLE
AUXILIARY DEVICE ENABLE
DECODER
0
R1 LOOK-UP
TABLE
EN
SEL
80h
C7h
TABLE 03TABLE 02TABLE 01
Figure 2. Memory Organization, ADEN = 0
MAIN
DEVICE
MON LOOK-UP
TABLE CONTROL
R0 LOOK-UP
TABLE
AUXILIARY
DEVICE
80h
DEC
0
95
96
127
128
143
199
255
EN
EN
EN
EN
SEL
EN
SEL
FFh
7Fh
80h
80h
C7h
8Fh
TABLE SELECT
TABLE 00
MAIN DEVICE ENABLE
DECODER
0
R1 LOOK-UP
TABLE
EN
SEL
80h
C7h
TABLE 03TABLE 02TABLE 01
MEMORY PARTITION WITH ADEN BIT = 1
RESERVED RESERVED
5Fh
60h
Figure 3. Memory Organization, ADEN = 1
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