Interfacing with LVPECL Outputs
The equivalent LVPECL output circuit is given in Figure
7. This output is designed to drive a pair of 50Ω trans-
mission lines terminated with 50Ω to V
TT
= V
CC
- 2V. If
a separate termination voltage (V
TT
) is not available,
other termination methods can be used such as shown
in Figures 5 and 6. Unused outputs should be disabled
and may be left open. For more information on LVPECL
terminations and how to interface with other logic fami-
lies, refer to Maxim Application Note
HFAN-01.0:
Introduction to LVDS, PECL, and CML
.
Interface Models
Figure 7 and Figure 8 show examples of interface models.
MAX3622
Figure 4. Crystal, Capacitors Connection
Low-Jitter, Precision Clock Generator
with Two Outputs
_______________________________________________________________________________________ 7
NOTE: AC-COUPLING IS OPTIONAL.
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