
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
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V
ILmax
t
HIGH
t
LOW
t
T
t
R
t
F
V
IHmin
PCLK_IN
Figure 2. Parallel Clock Requirements
OUT-
C
L
C
L
R
L
OUT+
t
FALL
20%20%
(OUT+) - (OUT-)
80%
80%
t
RISE
Figure 3. Output Rise and Fall Times
V
IHmin
V
IHmin
V
IHmin
V
ILmax
V
ILmax
V
ILmax
PCLK_IN
RGB_IN[17:0]
CNTL_IN[8:0]
DE_IN
t
HOLD
t
SET
Figure 4. Synchronous Input Timing
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