Rainbow-electronics ATtiny26L Manuel d'utilisateur télécharger pdf (Page 93)

ATtiny26(L)

1477B–AVR–04/02

signal transition on the pin will be delayed between ½ and 1½ system clock period

depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as

indicated in Figure 56. The out instruction sets the “SYNC LATCH” signal at the positive

edge of the clock. In this case, the delay t

through the synchronizer is one system

clock period.

Figure 56. Synchronization when Reading a Software Assigned Pin Value

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

1 2 ... 88 89 90 91 92 93 94 95 96 97 98 ... 150 151

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Rainbow-electronics ATtiny26L Manuel d'utilisateur Page 93