Rainbow-electronics T89C51AC2 Manuel d'utilisateur télécharger pdf (Page 87)

T89C51AC2

Rev. B – 19-Dec-01

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register. This register also contains a global disable bit

which must be cleared to disable all the interrupts at the same time.

Each interrupt source can also be individually programmed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the

bit values and priority levels associated with each combination.

Table 49. Priority Level Bit Values

A low-priority interrupt can be interrupted by a high priority interrupt but not by another

low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of the higher priority level is serviced. If interrupt requests of the same priority

level are received simultaneously, an internal polling sequence determines which

request is serviced. Thus within each priority level there is a second priority structure

determined by the polling sequence, see Table 50.

Table 50. Interrupt priority Within level

IPH.x IPL.x Interrupt Level Priority

0 0 0 (Lowest)

011

102

1 1 3 (Highest)

Interrupt Name Interrupt Address Vector Priority Number

external interrupt (INT0) 0003h 1

Timer0 (TF0) 000Bh 2

external interrupt (INT1) 0013h 3

Timer1 (TF1) 001Bh 4

PCA (CF or CCFn) 0033h 5

UART (RI or TI) 0023h 6

Timer2 (TF2) 002Bh 7

ADC (ADCI) 0043h 9

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 109 110

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Rainbow-electronics T89C51AC2 Manuel d'utilisateur Page 87