Rainbow-electronics ATtiny10 Manuel d'utilisateur

Features• High Performance, Low Power AVR® 8-Bit Microcontroller• Advanced RISC Architecture– 54 Powerful Instructions – Most Single Clock Cycle Execu

108127B–AVR–08/09ATtiny4/5/9/10Figure 4-4. The Parallel Instruction Fetches and Instruction ExecutionsFigure 4-4 shows the parallel instruction fetche

1008127B–AVR–08/09ATtiny4/5/9/1014.3.9 Collision Detection ExceptionThe TPI physical layer uses one bi-directional data line for both data reception a

1018127B–AVR–08/09ATtiny4/5/9/10The TPI access layer controls the character transfer direction on the TPI physical layer. It alsohandles the recovery

1028127B–AVR–08/09ATtiny4/5/9/1014.5 Instruction SetThe TPI has a compact instruction set that is used to access the TPI Control and Status Space(CSS)

1038127B–AVR–08/09ATtiny4/5/9/1014.5.2 SST - Serial STore to data space using indirect addressingThe SST instruction uses indirect addressing to store

1048127B–AVR–08/09ATtiny4/5/9/1014.5.6 SLDCS - Serial LoaD data from Control and Status space using direct addressingThe SLDCS instruction loads data

1058127B–AVR–08/09ATtiny4/5/9/1014.7 Control and Status Space Register DescriptionsThe control and status registers of the Tiny Programming Interface

1068127B–AVR–08/09ATtiny4/5/9/10• Bits 2:0 – GT[2:0]: Guard TimeThese bits specify the number of additional IDLE bits that are inserted to the idle ti

1078127B–AVR–08/09ATtiny4/5/9/1015. Memory Programming15.1 Features• Two Embedded Non-Volatile Memories:– Non-Volatile Memory Lock bits (NVM Lock bits

1088127B–AVR–08/09ATtiny4/5/9/1015.3 Non-Volatile MemoriesThe ATtiny4/5/9/10 have the following, embedded NVM:• Non-Volatile Memory Lock Bits• Flash m

1098127B–AVR–08/09ATtiny4/5/9/1015.3.2 Flash MemoryThe embedded Flash memory of ATtiny4/5/9/10 has four separate sections, as shown in Table15-3 and T

118127B–AVR–08/09ATtiny4/5/9/10interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when aReturn from Interrupt

1108127B–AVR–08/09ATtiny4/5/9/10Configuration bits are not affected by a chip erase but they can be cleared using the configura-tion section erase com

1118127B–AVR–08/09ATtiny4/5/9/1015.3.5.1 Latching of Calibration ValueTo ensure correct frequency of the calibrated internal oscillator the calibratio

1128127B–AVR–08/09ATtiny4/5/9/10Figure 15-1. Addressing the Flash Memory 15.4.2 Reading the Flash The Flash can be read from the data memory mapped lo

1138127B–AVR–08/09ATtiny4/5/9/10Before starting the Chip erase, the NVMCMD register must be loaded with the CHIP_ERASEcommand. To start the erase oper

1148127B–AVR–08/09ATtiny4/5/9/1015.4.4 Reading NVM Lock BitsThe Non-Volatile Memory Lock Byte can be read from the mapped location in data memory.15.4

1158127B–AVR–08/09ATtiny4/5/9/1015.7 Register Description15.7.1 NVMCSR - Non-Volatile Memory Control and Status Register• Bit 7 - NVMBSY: Non-Volatil

1168127B–AVR–08/09ATtiny4/5/9/1016. Electrical Characteristics16.1 Absolute Maximum Ratings*16.2 DC CharacteristicsOperating Temperature...

1178127B–AVR–08/09ATtiny4/5/9/10Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AV

1188127B–AVR–08/09ATtiny4/5/9/1016.4 Clock Characteristics16.4.1 Accuracy of Calibrated Internal OscillatorIt is possible to manually calibrate the in

1198127B–AVR–08/09ATtiny4/5/9/1016.5 System and Reset CharacteristicsNote: 1. Values are guidelines, only16.5.1 Power-On ResetNote: 1. Values are guid

128127B–AVR–08/09ATtiny4/5/9/104.8 Register Description4.8.1 CCP – Configuration Change Protection Register• Bits 7:0 – CCP[7:0] – Configuration Chang

1208127B–AVR–08/09ATtiny4/5/9/1016.6 Analog Comparator CharacteristicsNote: All parameters are based on simulation results. None are tested in product

1218127B–AVR–08/09ATtiny4/5/9/1016.8 Serial Programming CharacteristicsFigure 16-3. Serial Programming TimingTable 16-9. Serial Programming Characteri

1228127B–AVR–08/09ATtiny4/5/9/1017. Typical CharacteristicsThe data contained in this section is largely based on simulations and characterization of

1238127B–AVR–08/09ATtiny4/5/9/1017.2 ATtiny4/5/9/1017.2.1 Active Supply CurrentFigure 17-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)Fig

1248127B–AVR–08/09ATtiny4/5/9/10Figure 17-3. Active Supply Current vs. VCC (Internal Oscillator, 8 MHz)Figure 17-4. Active Supply Current vs. VCC (Int

1258127B–AVR–08/09ATtiny4/5/9/10Figure 17-5. Active Supply Current vs. VCC (Internal Oscillator, 128 kHz)Figure 17-6. Active Supply Current vs. VCC (E

1268127B–AVR–08/09ATtiny4/5/9/1017.2.2 Idle Supply CurrentFigure 17-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz)Figure 17-8. Idle Supply C

1278127B–AVR–08/09ATtiny4/5/9/10Figure 17-9. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz)Figure 17-10. Idle Supply Current vs. VCC (Intern

1288127B–AVR–08/09ATtiny4/5/9/1017.2.3 Power-down Supply CurrentFigure 17-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)Figure 17-12.

1298127B–AVR–08/09ATtiny4/5/9/1017.2.4 Pin Pull-upFigure 17-13. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)Figure 17-14. I/O Pin P

138127B–AVR–08/09ATtiny4/5/9/10The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-nation for the operated b

1308127B–AVR–08/09ATtiny4/5/9/10Figure 17-15. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)Figure 17-16. Reset Pull-up Resistor Curren

1318127B–AVR–08/09ATtiny4/5/9/10Figure 17-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)Figure 17-18. Reset Pull-up Resistor Cu

1328127B–AVR–08/09ATtiny4/5/9/1017.2.5 Pin Driver StrengthFigure 17-19. I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V)Figure 17-20. I/O Pin Outp

1338127B–AVR–08/09ATtiny4/5/9/10Figure 17-21. I/O pin Output Voltage vs. Sink Current (VCC = 5V)Figure 17-22. I/O Pin Output Voltage vs. Source Curren

1348127B–AVR–08/09ATtiny4/5/9/10Figure 17-23. I/O Pin Output Voltage vs. Source Current (VCC = 3V)Figure 17-24. I/O Pin output Voltage vs. Source Curr

1358127B–AVR–08/09ATtiny4/5/9/10Figure 17-25. Reset Pin as I/O, Output Voltage vs. Sink CurrentFigure 17-26. Reset Pin as I/O, Output Voltage vs. Sour

1368127B–AVR–08/09ATtiny4/5/9/1017.2.6 Pin Threshold and HysteresisFigure 17-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’)Figu

1378127B–AVR–08/09ATtiny4/5/9/10Figure 17-29. I/O Pin Input Hysteresis vs. VCCFigure 17-30. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIH, I/

1388127B–AVR–08/09ATtiny4/5/9/10Figure 17-31. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’)Figure 17-32. Reset Pin, Inp

1398127B–AVR–08/09ATtiny4/5/9/10Figure 17-33. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’)Figure 17-34. Reset Input Threshold Volt

148127B–AVR–08/09ATtiny4/5/9/105. MemoriesThis section describes the different memories in the ATtiny4/5/9/10. Devices have two mainmemory areas, the

1408127B–AVR–08/09ATtiny4/5/9/10Figure 17-35. Reset Input Hysteresis vs. VCC (Reset Pin Used as I/O)17.2.7 Analog Comparator OffsetFigure 17-36. Analo

1418127B–AVR–08/09ATtiny4/5/9/1017.2.8 Internal Oscillator SpeedFigure 17-37. Watchdog Oscillator Frequency vs. VCCFigure 17-38. Watchdog Oscillator F

1428127B–AVR–08/09ATtiny4/5/9/10Figure 17-39. Calibrated Oscillator Frequency vs. VCCFigure 17-40. Calibrated Oscillator Frequency vs. TemperatureCALI

1438127B–AVR–08/09ATtiny4/5/9/10Figure 17-41. Calibrated Oscillator Frequency vs, OSCCAL Value17.2.9 VLM ThresholdsFigure 17-42. VLM1L Threshold of VC

1448127B–AVR–08/09ATtiny4/5/9/10Figure 17-43. VLM1H Threshold of VCC Level MonitorFigure 17-44. VLM2 Threshold of VCC Level MonitorVLM THRESHOLD vs. T

1458127B–AVR–08/09ATtiny4/5/9/10Figure 17-45. VLM3 Threshold of VCC Level Monitor17.2.10 Current Consumption of Peripheral UnitsFigure 17-46. ADC Curr

1468127B–AVR–08/09ATtiny4/5/9/10Figure 17-47. Analog Comparator Current vs. VCCFigure 17-48. VCC Level Monitor Current vs. VCCANALOG COMPARATOR CURREN

1478127B–AVR–08/09ATtiny4/5/9/10Figure 17-49. Temperature Dependence of VLM Current vs. VCCFigure 17-50. Watchdog Timer Current vs. VCCVLM SUPPLY CURR

1488127B–AVR–08/09ATtiny4/5/9/1017.2.11 Current Consumption in Reset and Reset PulsewidthFigure 17-51. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, ex

1498127B–AVR–08/09ATtiny4/5/9/1018. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page0x3F SREG I T H S V N Z C Page 12

158127B–AVR–08/09ATtiny4/5/9/10Figure 5-1. Data Memory Map (Byte Addressing) 5.2.1 Data Memory Access TimesThis section describes the general access t

1508127B–AVR–08/09ATtiny4/5/9/10Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memo

1518127B–AVR–08/09ATtiny4/5/9/1019. Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD

1528127B–AVR–08/09ATtiny4/5/9/10BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1SBI A, b Set Bit in I/O Register I/O(A, b) ← 1None1CBI A, b Clear Bit in I/O R

1538127B–AVR–08/09ATtiny4/5/9/1020. Ordering InformationNotes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sale

1548127B–AVR–08/09ATtiny4/5/9/10Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed or

1558127B–AVR–08/09ATtiny4/5/9/10Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed or

1568127B–AVR–08/09ATtiny4/5/9/10Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed or

1578127B–AVR–08/09ATtiny4/5/9/1021. Packaging Information21.1 6ST1TITLE DRAWING NO. GPCREV. Package Drawing Contact: [email protected]

1588127B–AVR–08/09ATtiny4/5/9/1022. ErrataThe revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10device.22.1 AT

1598127B–AVR–08/09ATtiny4/5/9/1023. Datasheet Revision History23.1 Rev. 8127B – 08/091. Updated document template2. Expanded document to also cover de

168127B–AVR–08/09ATtiny4/5/9/10All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may beaccessed using the LD and

1608127B–AVR–08/09ATtiny4/5/9/10

i8127B–AVR–08/09ATtiny4/5/9/10Table of ContentsFeatures...

ii8127B–AVR–08/09ATtiny4/5/9/107.3 Minimizing Power Consumption ...247.4 Register

iii8127B–AVR–08/09ATtiny4/5/9/1013.4 Starting a Conversion ...8413.

iv8127B–AVR–08/09ATtiny4/5/9/1017.1 Supply Current of I/O Modules ...12217.2 ATtin

v8127B–AVR–08/09ATtiny4/5/9/10

8127B–AVR–08/09Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel AsiaU

178127B–AVR–08/09ATtiny4/5/9/106. Clock SystemFigure 6-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of thecloc

188127B–AVR–08/09ATtiny4/5/9/106.1.4 ADC Clock – clkADCThe ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocksin

198127B–AVR–08/09ATtiny4/5/9/106.2.3 Internal 128 kHz OscillatorThe internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz

28127B–AVR–08/09ATtiny4/5/9/101. Pin ConfigurationsFigure 1-1. Pinout of ATtiny4/5/9/101.1 Pin Description1.1.1 VCCSupply voltage.1.1.2 GNDGround.1.1.

208127B–AVR–08/09ATtiny4/5/9/106.4 Starting6.4.1 Starting from ResetThe internal reset is immediately asserted when a reset source goes active. The in

218127B–AVR–08/09ATtiny4/5/9/106.5 Register Description6.5.1 CLKMSR – Clock Main Settings Register• Bit 7:2 – Res: Reserved BitsThese bits are reserve

228127B–AVR–08/09ATtiny4/5/9/106.5.3 CLKPSR – Clock Prescale Register• Bits 7:4 – Res: Reserved BitsThese bits are reserved and will always read as ze

238127B–AVR–08/09ATtiny4/5/9/107. Power Management and Sleep ModesThe high performance and industry leading code efficiency makes the AVR microcontrol

248127B–AVR–08/09ATtiny4/5/9/10analog comparator can be powered down by setting the ACD bit in “ACSR – Analog ComparatorControl and Status Register” o

258127B–AVR–08/09ATtiny4/5/9/107.3.1 Analog ComparatorWhen entering Idle mode, the analog comparator should be disabled if not used. In the power-down

268127B–AVR–08/09ATtiny4/5/9/10• Bits 3:1 – SM2..SM0: Sleep Mode Select Bits 2..0These bits select between available sleep modes, as shown in Table 7-

278127B–AVR–08/09ATtiny4/5/9/108. System Control and Reset8.1 Resetting the AVRDuring reset, all I/O registers are set to their initial values, and th

288127B–AVR–08/09ATtiny4/5/9/108.2.1 Power-on ResetA Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection levelis de

298127B–AVR–08/09ATtiny4/5/9/10The VLM can also be used to improve reset characteristics at falling supply. Without VLM, thePower-On Reset (POR) does

38127B–AVR–08/09ATtiny4/5/9/102. OverviewATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVRenhanced RISC architecture.

308127B–AVR–08/09ATtiny4/5/9/10Figure 8-5. Watchdog Reset During Operation8.3 Watchdog TimerThe Watchdog Timer is clocked from an on-chip oscillator,

318127B–AVR–08/09ATtiny4/5/9/108.3.1 Procedure for Changing the Watchdog Timer ConfigurationThe sequence for changing configuration differs between th

328127B–AVR–08/09ATtiny4/5/9/108.4 Register Description8.4.1 WDTCSR – Watchdog Timer Control and Status Register• Bit 7 – WDIF: Watchdog Timer Interru

338127B–AVR–08/09ATtiny4/5/9/10• Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0The WDP3..0 bits determine the Watchdog Timer prescaling

348127B–AVR–08/09ATtiny4/5/9/10• Bits 2:0 – VLM2:0: Trigger Level of Voltage Level MonitorThese bits set the trigger level for the voltage level monit

358127B–AVR–08/09ATtiny4/5/9/109. InterruptsThis section describes the specifics of the interrupt handling in ATtiny4/5/9/10. For a generalexplanation

368127B–AVR–08/09ATtiny4/5/9/10<continued>0x000B RESET: ldi r16, high(RAMEND); Main program start0x000C out SPH,r16 ; Set Stack Pointer0x000D l

378127B–AVR–08/09ATtiny4/5/9/10Figure 9-1. Timing of pin change interrupts9.3 Register Description9.3.1 EICRA – External Interrupt Control Register AT

388127B–AVR–08/09ATtiny4/5/9/10selected, the low level must be held until the completion of the currently executing instruction togenerate an interrup

398127B–AVR–08/09ATtiny4/5/9/109.3.4 PCICR – Pin Change Interrupt Control Register• Bits 7:1 – Res: Reserved BitsThese bits are reserved and will alwa

48127B–AVR–08/09ATtiny4/5/9/10The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System ProgrammableFlash, 32 bytes of SRAM, four

408127B–AVR–08/09ATtiny4/5/9/1010. I/O Ports10.1 OverviewAll AVR ports have true Read-Modify-Write functionality when used as general digital I/O port

418127B–AVR–08/09ATtiny4/5/9/1010.2 Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 sh

428127B–AVR–08/09ATtiny4/5/9/10The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,Pxn is configured as

438127B–AVR–08/09ATtiny4/5/9/10Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode10.2.4 Reading the Pin ValueIndependent of the

448127B–AVR–08/09ATtiny4/5/9/10When reading back a software assigned pin value, a nop instruction must be inserted as indi-cated in Figure 10-5 on pag

458127B–AVR–08/09ATtiny4/5/9/1010.2.7 Program ExampleThe following code example shows how to set port B pin 0 high, pin 1 low, and define the portpins

468127B–AVR–08/09ATtiny4/5/9/10Figure 10-6. Alternate Port Functions(1)Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins with

478127B–AVR–08/09ATtiny4/5/9/10Table 10-2 on page 47 summarizes the function of the overriding signals. The pin and portindexes from Figure 10-6 on pa

488127B–AVR–08/09ATtiny4/5/9/1010.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-3 on page 48.• Port

498127B–AVR–08/09ATtiny4/5/9/10• OC0B: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B

58127B–AVR–08/09ATtiny4/5/9/103. General Information3.1 ResourcesA comprehensive set of drivers, application notes, data sheets and descriptions on de

508127B–AVR–08/09ATtiny4/5/9/10Notes: 1. EXT_CLOCK is 1 when external clock is selected as main clock.10.4 Register Description10.4.1 PORTCR – Port Co

518127B–AVR–08/09ATtiny4/5/9/1010.4.3 PORTB – Port B Data Register10.4.4 DDRB – Port B Data Direction Register10.4.5 PINB – Port B Input PinsBit 76543

528127B–AVR–08/09ATtiny4/5/9/1011. 16-bit Timer/Counter011.1 Features• True 16-bit Design, Including 16-bit PWM• Two Independent Output Compare Units•

538127B–AVR–08/09ATtiny4/5/9/10A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 11-1 on page 52. Foractual placement of I/O p

548127B–AVR–08/09ATtiny4/5/9/1011.3 Clock SourcesThe Timer/Counter can be clocked by an internal or an external clock source. The clock sourceis selec

558127B–AVR–08/09ATtiny4/5/9/10clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-tem clock cycles, where

568127B–AVR–08/09ATtiny4/5/9/10Figure 11-4. Counter Unit Block DiagramSignal description (internal signals):Count Increment or decrement TCNT0 by 1.Di

578127B–AVR–08/09ATtiny4/5/9/1011.5 Input Capture UnitThe Timer/Counter incorporates an Input Capture unit that can capture external events and giveth

588127B–AVR–08/09ATtiny4/5/9/10tion mode (WGM03:0) bits must be set before the TOP value can be written to the ICR0Register. When writing the ICR0 Reg

598127B–AVR–08/09ATtiny4/5/9/10cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,the clearing of the I

68127B–AVR–08/09ATtiny4/5/9/104. CPU CoreThis section discusses the AVR core architecture in general. The main function of the CPU coreis to ensure co

608127B–AVR–08/09ATtiny4/5/9/10double buffering is disabled. The double buffering synchronizes the update of the OCR0x Com-pare Register to either TOP

618127B–AVR–08/09ATtiny4/5/9/1011.7 Compare Match Output UnitThe Compare Output Mode (COM0x1:0) bits have two functions. The Waveform Generator usesth

628127B–AVR–08/09ATtiny4/5/9/1011.7.1 Compare Output Mode and Waveform GenerationThe Waveform Generator uses the COM0x1:0 bits differently in normal,

638127B–AVR–08/09ATtiny4/5/9/10The timing diagram for the CTC mode is shown in Figure 11-8 on page 63. The counter value(TCNT0) increases until a comp

648127B–AVR–08/09ATtiny4/5/9/10operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor-rect and phase and freque

658127B–AVR–08/09ATtiny4/5/9/10The procedure for updating ICR0 differs from updating OCR0A when used for defining the TOPvalue. The ICR0 Register is n

668127B–AVR–08/09ATtiny4/5/9/10operation. However, due to the symmetric feature of the dual-slope PWM modes, these modesare preferred for motor contro

678127B–AVR–08/09ATtiny4/5/9/10Compare Registers, a compare match will never occur between the TCNT0 and the OCR0x.Note that when using fixed TOP valu

688127B–AVR–08/09ATtiny4/5/9/10the maximum resolution is 16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits canbe calculated using the foll

698127B–AVR–08/09ATtiny4/5/9/10Using the ICR0 Register for defining TOP works well when using fixed TOP values. By usingICR0, the OCR0A Register is fr

78127B–AVR–08/09ATtiny4/5/9/10Six of the 16 registers can be used as three 16-bit indirect address register pointers for dataspace addressing – enabli

708127B–AVR–08/09ATtiny4/5/9/10Figure 11-13. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)Figure 11-14 on page 70 shows

718127B–AVR–08/09ATtiny4/5/9/10Figure 11-15. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)11.10 Accessing 16-bit RegistersThe TCNT0, OCR0A

728127B–AVR–08/09ATtiny4/5/9/10Note: See “Code Examples” on page 5.The code example returns the TCNT0 value in the r17:r16 register pair.It is importa

738127B–AVR–08/09ATtiny4/5/9/10Note: See “Code Examples” on page 5.The code example requires that the r17:r16 register pair contains the value to be w

748127B–AVR–08/09ATtiny4/5/9/10When OC0A or OC0B is connected to the pin, the function of COM0x1:0 bits depends on theWGM03:0 bits. Table 11-2 shows t

758127B–AVR–08/09ATtiny4/5/9/10• Bits 1:0 – WGM01:0: Waveform Generation ModeCombined with WGM03:2 bits of TCCR0B, these bits control the counting seq

768127B–AVR–08/09ATtiny4/5/9/10When a capture is triggered according to the ICES0 setting, the counter value is copied into theInput Capture Register

778127B–AVR–08/09ATtiny4/5/9/10The OC0A/OC0B output is changed according to its COM0x1:0 bits setting. Note that theFOC0A/FOC0B bits are implemented a

788127B–AVR–08/09ATtiny4/5/9/108-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Ac

798127B–AVR–08/09ATtiny4/5/9/1011.11.9 TIFR0 – Timer/Counter Interrupt Flag Register 0• Bits 7:6, 4:3 – Reserved BitsThese bits are reserved for futur

88127B–AVR–08/09ATtiny4/5/9/104.4 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to a

808127B–AVR–08/09ATtiny4/5/9/10This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-ing during configuration

818127B–AVR–08/09ATtiny4/5/9/1012. Analog ComparatorThe Analog Comparator compares the input values on the positive pin AIN0 and negative pinAIN1. Whe

828127B–AVR–08/09ATtiny4/5/9/10• Bit 4 – ACI: Analog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the

838127B–AVR–08/09ATtiny4/5/9/1013. Analog to Digital Converter13.1 Features• 8-bit Resolution• 0.5 LSB Integral Non-linearity• ± 1 LSB Absolute Accura

848127B–AVR–08/09ATtiny4/5/9/10Figure 13-1. Analog to Digital Converter Block Schematic13.4 Starting a ConversionMake sure the ADC is powered by clear

858127B–AVR–08/09ATtiny4/5/9/10Figure 13-2. ADC Auto Trigger LogicUsing the ADC interrupt flag as a trigger source makes the ADC start a new conversio

868127B–AVR–08/09ATtiny4/5/9/10switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as theADEN bit is set, and is co

878127B–AVR–08/09ATtiny4/5/9/10Figure 13-6. ADC Timing Diagram, Auto Triggered ConversionIn Free Running mode (see Figure 13-7), a new conversion will

888127B–AVR–08/09ATtiny4/5/9/1013.6 Changing ChannelThe MUXn bits in the ADMUX Register are single buffered through a temporary register to whichthe C

898127B–AVR–08/09ATtiny4/5/9/10• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC con

98127B–AVR–08/09ATtiny4/5/9/10Figure 4-3. The X-, Y-, and Z-registersIn different addressing modes these address registers function as automatic incre

908127B–AVR–08/09ATtiny4/5/9/1013.9 Noise Canceling TechniquesDigital circuitry inside and outside the device generates EMI which might affect the acc

918127B–AVR–08/09ATtiny4/5/9/10• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0xFE to 0xFF

928127B–AVR–08/09ATtiny4/5/9/10• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent t

938127B–AVR–08/09ATtiny4/5/9/1013.12 Register Description13.12.1 ADMUX – ADC Multiplexer Selection Register• Bits 7:2 – Res: Reserved BitsThese bits a

948127B–AVR–08/09ATtiny4/5/9/10• Bit 4 – ADIF: ADC Interrupt FlagThis bit is set when an ADC conversion completes and the data registers are updated.

958127B–AVR–08/09ATtiny4/5/9/10trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Runningmode (ADTS[2:0]=0) wil

968127B–AVR–08/09ATtiny4/5/9/1014. Programming interface14.1 Features• Physical Layer:– Synchronous Data Transfer– Bi-directional, Half-duplex Receive

978127B–AVR–08/09ATtiny4/5/9/10The TPI is accessed via three pins, as follows:RESET: Tiny Programming Interface enable inputTPICLK: Tiny Programming I

988127B–AVR–08/09ATtiny4/5/9/1014.3.2 DisablingProvided that the NVM enable bit has been cleared, the TPI is automatically disabled if theRESET pin is

998127B–AVR–08/09ATtiny4/5/9/1014.3.6 OperationThe TPI physical layer operates synchronously on the TPICLK provided by the external pro-grammer. The d