Rainbow-electronics ATA6823 Manuel d'utilisateur

Naviguer en ligne ou télécharger Manuel d'utilisateur pour Logiciel Rainbow-electronics ATA6823. Rainbow Electronics ATA6823 User Manual Manuel d'utilisatio

  • Télécharger
  • Ajouter à mon manuel
  • Imprimer
  • Page
    / 28
  • Table des matières
  • MARQUE LIVRES
  • Noté. / 5. Basé sur avis des utilisateurs
Vue de la page 0
Features
PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors
A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge
Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS
5V/3.3V Regulator and Current Limitation Function
Reset Derived From 5V/3.3V Regulator Output Voltage
Sleep Mode With Supply Current of Typically < 45 µA, Wake-up by Signal on Pins EN2
or on LIN Interface
A Programmable Window Watchdog
Battery Overvoltage Protection and Battery Undervoltage Management
Overtemperature Warning and Protection (Shutdown)
LIN 2.0 Compliant
3.3V/5V Regulator with Trimmed Band Gap
QFN32 Package
1. Description
The ATA6823 is designed for several body and powertrain applications. The IC is
used to drive a continuous current motor in a full H-bridge configuration. An external
microcontroller controls the driving function of the IC by providing a PWM signal and a
direction signal and allows the use of the IC in a motor-control application. The PWM
control is performed by the low-side switch; the high-side switch is permanently on in
the driving phase. The VMODE configuration pin can be set to 5V or 3.3V mode (for
regulator and interface high level). The window watchdog has a programmable time,
programmable by choosing a certain value of the external watchdog resistor RWD,
internally trimmed to an accuracy of 10%. For communication a LIN transceiver 2.0 is
integrated.
H-bridge Motor
Driver
ATA6823
Preliminary
4856E–AUTO–07/07
Vue de la page 0
1 2 3 4 5 6 ... 27 28

Résumé du contenu

Page 1 - Preliminary

Features• PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors• A Programmable Dead Time Is Included to Avoid Peak Current

Page 2

104856E–AUTO–07/07ATA6823 [Preliminary] After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. Thereset output, /RES

Page 3

114856E–AUTO–07/07ATA6823 [Preliminary]5.6.1 Transmit ModeDuring transmission, the data at the pin TX will be transferred to the bus driver to generat

Page 4

124856E–AUTO–07/07ATA6823 [Preliminary] 5.7 Control Inputs EN1, EN2, DIR, PWM5.7.1 Pins EN1, EN2Any of the enable pins may be used to activate the IC

Page 5

134856E–AUTO–07/07ATA6823 [Preliminary]5.8 VG RegulatorThe VG regulator is used to generate the gate voltage for the low-side driver. Its output volta

Page 6

144856E–AUTO–07/07ATA6823 [Preliminary] Figure 5-5. Timing of the Drivers The delays tHxLH and tLxLH include the cross conduction time tCC.5.12 Short

Page 7

154856E–AUTO–07/07ATA6823 [Preliminary]6. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent da

Page 8

164856E–AUTO–07/07ATA6823 [Preliminary] 7. Thermal ResistanceParameters Symbol Value UnitThermal resistance junction to heat slug Rthjc<5 K/WTherma

Page 9

174856E–AUTO–07/07ATA6823 [Preliminary]9. Electrical CharacteristicsAll parameters given are valid for 7V ≤ VBAT ≤ 18V and for –40°C ≤ϑambient ≤ 125°C

Page 10 - ATA6823 [Preliminary]

184856E–AUTO–07/07ATA6823 [Preliminary] 2.9 HIGH threshold VMODE 1 VMODE H 4.0 V A2.10 LOW threshold VMODE 1 VMODE L 0.7 V A3 Reset and Watchdog3.1VC

Page 11

194856E–AUTO–07/07ATA6823 [Preliminary]3.15 Open window(5)t2780 × TOSCA3.16Output low-voltage of /RESETAt IOLRES = 1 mA 5 VOLRES0.4 V A3.17Internal p

Page 12

24856E–AUTO–07/07ATA6823 [Preliminary] Figure 1-1. Block Diagram VMODE /RESETMicrocontrollerLogic ControlVCCEN1WD12VRegulatorVint 5VRegulatorOTP12 bit

Page 13

204856E–AUTO–07/07ATA6823 [Preliminary] 4.12Leakage current at ground lossControl unit disconnected from groundLoss of local ground must not affect co

Page 14

214856E–AUTO–07/07ATA6823 [Preliminary]6.3Period charge pump oscillatorT100911µsA6.4CP load current in VG without CP loadLoad = 0A IVGCPz100 µA D6.5CP

Page 15

224856E–AUTO–07/07ATA6823 [Preliminary] 7.12Static high-side switch output high-voltage pins H1, H2ILx = –10 µA(PWM = static)VHxHstat1(7)VVBAT + VVG –

Page 16

234856E–AUTO–07/07ATA6823 [Preliminary]7.27Switching level of tCC comparatorVswtcc0.653 × VVCC0.667 × VVCC0.68 × VVCCV7.28Short circuit detection v

Page 17

244856E–AUTO–07/07ATA6823 [Preliminary] 10. Schaffner and Electromagnetic Compatibility10.1 Transients on Power-supply Rail (Battery)The application (

Page 18

254856E–AUTO–07/07ATA6823 [Preliminary]Figure 10-3. Pulse 3a (Ri = 50Ω) Figure 10-4. Pulse 3b (Ri = 50Ω) Figure 10-5. Pulse 4 (Ri = 0.01Ω) V12V-200Vt1

Page 19

264856E–AUTO–07/07ATA6823 [Preliminary] 10.2 Transients on Pin LINTransients to these pins are coupled capacitively to the IC and are valid for the ap

Page 20

274856E–AUTO–07/07ATA6823 [Preliminary]13. Package Information 14. Revision History12. Ordering InformationExtended Type Number Package RemarksATA6823

Page 21

4856E–AUTO–07/07Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel Asia

Page 22

34856E–AUTO–07/07ATA6823 [Preliminary]2. Pin ConfigurationFigure 2-1. Pinning QFN32 Note: YWW Date code (Y = Year - above 2000, WW = week number)ATA6

Page 23

44856E–AUTO–07/07ATA6823 [Preliminary] 3. General Statement and Conventions• Parameter values given without tolerances are indicative only and not to

Page 24

54856E–AUTO–07/07ATA6823 [Preliminary]4. Application4.1 General RemarkThis chapter describes the principal application for which the ATA6823 was desig

Page 25

64856E–AUTO–07/07ATA6823 [Preliminary] 5.1.2 Voltage SupervisorThis block is intended to protect the IC and the external power MOS transistors against

Page 26

74856E–AUTO–07/07ATA6823 [Preliminary]Pulling the EN2 pin up to the VBAT level will drive the IC into Active mode. EN2 is debounced witha time constan

Page 27

84856E–AUTO–07/07ATA6823 [Preliminary] Figure 5-1. Wake-up by pin LIN VBATACTIVESLEEP45% VBATtdbtdbt < twake LINtwake LIN55% VBATttttEN1LINVBAT - 1

Page 28

94856E–AUTO–07/07ATA6823 [Preliminary]5.4 5V/3.3V VCC RegulatorThe 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic ca

Commentaires sur ces manuels

Pas de commentaire