Rainbow-electronics AT45DQ321 Manuel d'utilisateur

DS-45DQ321-031–DFLASH–12/2012Features Single 2.3V - 3.6V or 2.5V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 a

10AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012The CS pin must remain low during the loading of the opcode, the address bytes, and the r

11AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20125.8 Dual-output Read Array (3Bh Opcode)The Dual-output Read Array command is similar to t

12AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012The CS pin must remain low during the loading of the opcode, the address bytes, the dummy

13AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012To load data into a buffer using the binary buffer size (512 bytes), an opcode of 44h for

14AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20126.6 Main Memory Page Program through Buffer with Built-In EraseThe Main Memory Page Progr

15AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012The CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, th

16AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 6-1. Block Erase Addressing6.10 Sector EraseThe Sector Erase command can be used to

17AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 6-2. Sector Erase Addressing6.11 Chip EraseThe Chip Erase command allows the entire

18AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20126.12 Program/Erase SuspendIn some code and data storage applications, it may not be possi

19AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 6-4. Operations Allowed and Not Allowed During SuspendCommandOperation During Progr

2AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012DescriptionThe AT45DQ321 is a 2.3V or 2.5V minimum, serial-interface sequential access Fla

20AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20126.13 Program/Erase ResumeThe Program/Erase Resume command allows a suspended program or e

21AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20127. Sector ProtectionTwo protection methods, hardware and software controlled, are provide

22AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20127.1.2 Disable Sector Protection To disable the sector protection, a 4-byte command sequen

23AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 7-3. WP Pin and Protection StatusTable 7-3.WP Pin and Protection Status7.3 Sector

24AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20127.3.1 Erase Sector Protection Register In order to modify and change the values of the Se

25AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012clocked into a byte location of the Sector Protection Register, then the protection statu

26AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20127.3.4 About the Sector Protection RegisterThe Sector Protection Register is subject to a

27AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20128. Security Features8.1 Sector LockdownThe device incorporates a sector lockdown mechanis

28AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 8-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte ValueTable 8-4. Read Sector

29AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20128.2 Security RegisterThe device contains a specialized Security Register that can be used

3AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 1-1. Pin Configurations Symbol Name and FunctionAsserted StateTypeCSChip Select: As

30AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20128.2.2 Reading the Security RegisterTo read the Security Register, an opcode of 77h and th

31AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20129. Additional Commands9.1 Main Memory Page to Buffer TransferA page of data can be transf

32AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012program the data from the buffer back into same page of main memory. The operation is int

33AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 9-2. Status Register Format – Byte 2Note: 1. R = Readable only9.4.1 RDY/BUSY BitThe

34AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20129.4.6 EPE Bit The EPE bit indicates whether the last erase or program operation completed

35AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 9-1. Configuration Register FormatNote: 1. Only bit seven of the Configuration Reg

36AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20129.6 Write Configuration RegisterThe Write Configuration Register commands are used to mod

37AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20129.6.2 Quad Disable CommandThe Quad Disable command is used to program the QE bit of the n

38AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201210. Deep Power-DownDuring normal operation, the device will be placed in the standby mode

39AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201210.1 Resume from Deep Power-DownIn order to exit the Deep Power-Down mode and resume norm

4AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012WP (I/O2)Write Protect (I/O2): When the WP pin is asserted, all sectors specified for prot

40AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201210.2 Ultra-Deep Power-DownThe Ultra-Deep Power-Down mode allows the device to consume far

41AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201210.2.1 Exit Ultra-Deep Power-DownTo exit from the Ultra-Deep Power-Down mode, the CS pin

42AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201211. Buffer and Page Size ConfigurationThe memory array of DataFlash devices is actually l

43AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201212. Manufacturer and Device ID ReadIdentification information can be read from the device

44AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 12-1. Read Manufacturer and Device IDTable 12-3. EDI DataByte Number Bit 7 Bit 6 B

45AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201213. Software ResetIn some applications, it may be necessary to prematurely terminate a pr

46AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201214. Operation Mode SummaryThe commands described previously can be grouped into four diff

47AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201215. Command TablesTable 15-1. Read CommandsTable 15-2. Program and Erase CommandsCommand

48AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 15-3. Protection and Security CommandsTable 15-4. Additional CommandsCommand Opcode

49AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Table 15-5. Legacy Commands(1)(2)Note: 1. Legacy commands are not recommended for new des

5AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20122. Block DiagramFigure 2-1. Block DiagramFlash Memory ArrayI/O InterfaceSCKCSRESET

50AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Note: X = Dummy BitTable 15-7. Detailed Bit-level Addressing Sequence for Standard DataFl

51AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Note: P = Page Address Bit B = Byte/Buffer Address Bit X = Dummy Bit84h 1 0 0 0 0 1 0 0

52AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201216. Power-On/Reset StateWhen power is first applied to the device, or when recovering fro

53AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201217. System ConsiderationsThe serial interface is controlled by the Serial Clock (SCK), Se

54AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201218. Electrical Specifications18.1 Absolute Maximum Ratings*18.2 DC and AC Operating Range

55AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201218.3 DC Characteristics Notes: 1. Typical values measured at 3.0V at 25C.2. ICC2 during

56AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201218.4 AC CharacteristicsNote: 1. Values are based on device characterization, not 100% tes

57AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201218.5 Program and Erase CharacteristicsNotes: 1. Values are based on device characterizati

58AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201221. Utilizing the RapidS FunctionTo take advantage of the RapidS function's ability

59AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 21-2. Command Sequence for Read/Write Operations for Page Size 512 bytes (Except S

6AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20123. Memory ArrayTo provide optimal flexibility, the AT45DQ321 memory array is divided into

60AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201222. AC WaveformsFour different timing waveforms are shown in Figure 22-1 through Figure 2

61AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 22-3. Waveform 3 = RapidS Mode 0Figure 22-4. Waveform 4 = RapidS Mode 3CSSCKSISOtC

62AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201223. Write OperationsThe following block diagram and waveforms illustrate the various writ

63AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 23-4. Quad-input Buffer WriteFigure 23-5. Buffer to Main Memory Page ProgramI/O0(S

64AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201224. Read OperationsThe following block diagram and waveforms illustrate the various read

65AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 24-3. Main Memory Page to Buffer TransferData From the selected Flash Page is read

66AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201225. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3Figure 25-1. Continuous Array

67AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 25-4. Main Memory Page Read (Opcode D2h)Figure 25-5. Dual-output Read Array (Opcod

68AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 25-6. Quad-output Read Array (Opcode 6Bh)Figure 25-7. Buffer Read (Opcode D4h or D

69AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 25-8. Buffer Read – Low Frequency (Opcode D1h or D3h)Figure 25-9. Read Sector Prot

7AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20124. Device OperationThe device operation is controlled by instructions from the host proces

70AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 25-11.Read Security Register (Opcode 77h)Figure 25-12. Status Register Read (Opcod

71AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 25-14.Reset TimingNote: 1. The CS signal should be in the high state before the RE

72AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201226. Auto Page Rewrite FlowchartFigure 26-1. Algorithm for Programming or Re-programming o

73AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/2012Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array RandomlyNote

74AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201227. Ordering Information27.1 Ordering DetailDevice GradeH = Green, NiPdAu lead finish,

75AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201227.2 Ordering CodesNotes: 1. The shipping carrier suffix is not marked on the device.Orde

76AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201227.3 Ordering Codes (Binary Page Mode)Notes: 1. The shipping carrier suffix is not marked

77AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201227.4 8S2 – 8-lead EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:contact@ade

78AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201227.5 8MA1 – 8-pad UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected]

79AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201227.6 9CC1 – 9-ball UBGADRAWING NO. REV. GPCTITLEPackage Drawing Contact:contact@adestote

8AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20125. Read CommandsBy specifying the appropriate opcode, data can be read from the main memor

80AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/201228. Revision HistoryDoc. Rev. Date CommentsDS-45DQ321-031 12/2012 Initial document releas

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

9AT45DQ321 [ADVANCE DATASHEET]DS-45DQ321-031–DFLASH–12/20125.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode)This command can be used to rea