Rainbow-electronics AT90LS4433 Manuel d'utilisateur télécharger pdf (Page 19)

AT90S/LS4433

1042G–AVR–09/02

Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the

Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled

independent of the individual interrupt enable settings. The I-bit is cleared by hardware

after an interrupt has occurred and is set by the RETI instruction to enable subsequent

interrupts.

• Bit 6 – T: Bit Copy Storage

The Bit Copy Instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the Register File can be cop-

ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetical operations. See the

Instruction Set description for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-

ment Overflow Flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See

the Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result from an arithmetical or logical operation.

See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result from an arithmetical or logical operation. See the

Instruction Set description for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetical or logical operation. See the

Instruction Set description for detailed information.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

Bit 76543210

$3F ($5F) I THSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

InitialValue00000000

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 124 125

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