Rainbow-electronics ATmega163L Manuel d'utilisateur

1Features• High-performance, Low-power AVR® 8-bit Microcontroller– 130 Powerful Instructions - Most Single Clock Cycle Execution– 32 x 8 General Purpo

ATmega163(L)10In the different addressing modes these address registers have functions as fixed displacement, automatic increment anddecrement (see th

ATmega163(L)100n: 7,6…0, pin number.PORT A SchematicsNote that all port pins are synchronized. The synchronization latches are not shown in the figure

ATmega163(L)101The Port B pins with alternate functions are shown in Table 44.When the pins are used for the alternate function, the DDRB and PORTB re

ATmega163(L)102n: 7,6…0, pin number.Alternate Functions Of PORTBThe alternate pin configuration is as follows:•SCK - PORTB, Bit 7SCK: Master clock out

ATmega163(L)103Figure 64. PORTB Schematic Diagram (Pins PB0 and PB1)Figure 65. PORTB Schematic Diagram (Pins PB2 and PB3)2PUDPUD: PULL-UP DISABLEDAT

ATmega163(L)104Figure 66. PORTB Schematic Diagram (Pin PB4)Figure 67. PORTB Schematic Diagram (Pin PB5)DATA BUSDDQQRESETRESETCCWDWPRDMOSPULL-UPPB4SP

ATmega163(L)105Figure 68. PORTB Schematic Diagram (Pin PB6)Figure 69. PORTB Schematic Diagram (Pin PB7)DATA BUSDDQQRESETRESETCCWDWPRDMOSPULL-UPPB6RR

ATmega163(L)106Port CPort C is an 8-bit bi-directional I/O port with internal pull-ups.Three I/O memory address locations are allocated for the Port C

ATmega163(L)107n: 7…0, pin numberAlternate Functions of PORTC•TOSC2 - PORTC, Bit 7TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one)

ATmega163(L)108Figure 70. PORTC Schematic Diagram (Pins PC0 - PC1)Figure 71. PORTC Schematic Diagram (Pins PC2 - PC5)01TWENSCL/SDA inSCL/SDA outPCnD

ATmega163(L)109Figure 72. PORTC Schematic Diagram (Pins PC6)Figure 73. PORTC Schematic Diagram (Pins PC7)DATA BUSDDQQRESETRESETCCWDWPRDMOSPULL-UPPC6

ATmega163(L)11The lower 1120 Data Memory locations address the Register file, the I/O Memory, and the internal data SRAM. The first 96locations addres

ATmega163(L)110Port DPort D is an 8 bit bi-directional I/O port with internal pull-up resistors.Three I/O memory address locations are allocated for P

ATmega163(L)111pin has to be configured as an output pin, or the PUD bit has to be set. The Port D pins are tri-stated when a reset conditionbecomes a

ATmega163(L)112Figure 74. PORTD Schematic Diagram (Pin PD0)Figure 75. PORTD Schematic Diagram (Pin PD1)DATA BUSDDQQRESETRESETCCWDWPRDMOSPULL-UPPD0RX

ATmega163(L)113Figure 76. PORTD Schematic Diagram (Pins PD2 and PD3)Figure 77. PORTD Schematic Diagram (Pins PD4 and PD5)PUDPUD: PULL-UP DISABLEn:m:

ATmega163(L)114Figure 78. PORTD Schematic Diagram (Pin PD6)Figure 79. PORTD Schematic Diagram (Pin PD7)DATA BUSDDQQRESETRESETCCWDWPRDMOSPULL-UPPD6RR

ATmega163(L)115Memory ProgrammingBoot Loader SupportThe ATmega163 provides a mechanism for programming and reprogramming code by the MCU itself. This

ATmega163(L)116Figure 80. Memory SectionsEntering the Boot Loader ProgramThe SPM instruction can access the entire Flash, but can only be executed fr

ATmega163(L)117Capabilities of the Boot LoaderThe program code within the Boot Loader section has the capability to read from and write into the entir

ATmega163(L)118Wait for SPM Instruction to CompleteThough the CPU is halted during page write, page erase or Lock bit write, for future compatibility,

ATmega163(L)119Table 53. Boot Lock Bit1 Protection Modes (Boot Loader Section)‘1’ means unprogrammed, ‘0´means programmedSetting the Boot Loader Lock

ATmega163(L)12I/O DirectFigure 12. I/O Direct AddressingOperand address is contained in 6 bits of the instruction word. n is the destination or sourc

ATmega163(L)120EEPROM Write Prevents Writing to SPMCRNote that an EEPROM write operation will block all software programming to Flash. Reading the Fus

ATmega163(L)121•Bit 2 - PGWRT: Page WriteIf this bit is set at the same time as SPMEN, the next SPM instruction within four clock cycles executes page

ATmega163(L)122ldi spmcrval, (1<<ASRE) + (1<<SPMEN)call Do_spm; transfer data from RAM to Flash page bufferldi looplo, low(PAGESIZEB) ;ini

ATmega163(L)123rjmp Wait_spmretProgram And Data Memory Lock BitsThe ATmega163 provides six Lock bits which can be left unprogrammed (‘1’) or can be pr

ATmega163(L)124• CKSEL3..0 select the clock source and the start-up delay after reset, according to Table 1 on page 5 and Table 5 on page 22. Default

ATmega163(L)125Figure 81. Parallel ProgrammingATmega163VCC+5VGNDXTAL1PD1PD2PD3PD4PD5PD6 PB7 - PB0DATARESETPD7+12 VBS1XA0XA1OERDY/BSYPAGELPA0WRBS2Tabl

ATmega163(L)126Enter Programming ModeThe following algorithm puts the device in parallel programming mode:1. Apply 4.5 - 5.5V between VCC and GND.2. S

ATmega163(L)1274. Give XTAL1 a positive pulse. This loads the address low byte.C. Load Data Low Byte1. Set XA1, XA0 to ‘01’. This enables data loading

ATmega163(L)128Figure 82. Programming the Flash WaveformsFigure 83. Programming the Flash Waveforms (continued)Programming the EEPROMThe programming

ATmega163(L)1293. Wait until to RDY/BSY goes high before programming the next byte.(See Figure 84 for signal waveforms)The loaded command and address

ATmega163(L)13Data IndirectFigure 15. Data Indirect AddressingOperand address is the contents of the X, Y, or the Z-register.Data Indirect With Pre-d

ATmega163(L)130Programming the Fuse Low BitsThe algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 12

ATmega163(L)1313. Set OE to ‘0’, BS2 to ‘1’ and BS1 to ‘1’. The status of the Fuse High bits can now be read at DATA (‘0’ means pro-grammed).Bit 2..1

ATmega163(L)132Notes: 1. tWLRH is valid for the Write EEPROM, Write Fuse Bits and Write Lock Bits commands.2. tWLRH_CE is valid for the Chip Erase c

ATmega163(L)133Figure 86. Serial Programming and VerifyWhen programming the EEPROM, an auto-erase cycle is built into the self-timed programming oper

ATmega163(L)134positive pulse and issue a new Programming Enable command. If the $53 is not seen within 32 attempts, there is no functional device con

ATmega163(L)135Notes: 1. Includes variation over voltage and temperature after RC oscillator has been calibrated to 1.0 MHz2. Parallel EEPROM programm

ATmega163(L)136Note: a = address high bitsb = address low bitsH = 0 - Low byte, 1 - High Byteo = data outi = data inx = don’t care1 = lock bit 12 = lo

ATmega163(L)137Table 61. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 5.5V (Unless otherwise noted) Symbol Parameter Min Typ

ATmega163(L)138Electrical CharacteristicsAbsolute Maximum Ratings*DC CharacteristicsOperating Temperature... -55°C to +

ATmega163(L)139Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value where the pin is g

ATmega163(L)14Constant Addressing Using The LPM and SPM InstructionsFigure 18. Code Memory Constant AddressingConstant byte address is specified by t

ATmega163(L)140External Clock Drive WaveformsFigure 89. External Clock Drive WaveformsExternal Clock DriveNote: R should be in the range 3kΩ - 100kΩ,

ATmega163(L)141Notes: 1. In ATmega163, this parameter is characterized and not 100% tested.2. Required only for fSCL > 100 kHz.3. Cb = capacitance

ATmega163(L)142Figure 90. 2-wire Serial Bus TimingtSU;STAtLOWtHIGHtLOWtoftHD;STAtHD;DATtSU;DATtSU;STOtBUFSCLSDA

ATmega163(L)143Typical Characteristics - Preliminary DataAnalog comparator offset voltage is measured as absolute offset.Figure 91. Analog Comparator

ATmega163(L)144Figure 93. Analog Comparator Input Leakage Current (VCC = 6V; TA = 25°C)Figure 94. Watchdog Oscillator Frequency vs. VCCSink and sour

ATmega163(L)145Figure 95. Pull-up Resistor Current vs. Input Voltage (VCC = 5V)Figure 96. Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)020

ATmega163(L)146Figure 97. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)Figure 98. I/O Pin Source Current vs. Output Voltage (VCC = 5V)010203040

ATmega163(L)147Figure 99. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)Figure 100. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)I (

ATmega163(L)148Figure 101. I/O Pin Input Threshold vs. VCC (TA = 25°C)Figure 102. I/O Pin Input Hysteresis vs. VCC (TA = 25°C)00.511.522.52.7 4.0 5.

ATmega163(L)149Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z C 18$3E ($5E) SPH- - - -

ATmega163(L)15The EEPROM Data MemoryThe ATmega163 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which singleb

ATmega163(L)150Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses sho

ATmega163(L)151Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two Regist

ATmega163(L)152BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ←

ATmega163(L)153SEN Set Negative Flag N ← 1N1CLN Clear Negative Flag N ← 0 N 1SEZ Set Zero Flag Z ← 1Z1CLZ Clear Zero Flag Z ← 0 Z 1SEI Global Interr

ATmega163(L)154Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range4 2.7 - 5.5V ATmega163L-4ACATmega163L-4PC44A40P6Comme

ATmega163(L)155Packaging Information*Controlling Dimensions: Millimeters1.20(0.047) MAX10.10(0.394)9.90(0.386)SQ12.21(0.478)11.75(0.458)SQ0.75(0.030)0

© Atmel Corporation 2000.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

ATmega163(L)16Figure 23. On-chip Data SRAM Access CyclesI/O MemoryThe I/O space definition of the ATmega163 is shown in the following table:Table 2.

ATmega163(L)17$28 ($48) OCR1BL Timer/Counter1 Output Compare Register B Low-byte$27 ($47) ICR1H T/C 1 Input Capture Register High-byte$26 ($46) ICR1L

ATmega163(L)18Note: Reserved and unused locations are not shown in the table.All ATmega163 I/Os and peripherals are placed in the I/O space. The I/O l

ATmega163(L)19•Bit 2 - N: Negative FlagThe negative flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set De

ATmega163(L)2Pin Configurations(SCL)(SDA)(SDA)(SCL)

ATmega163(L)20Note: 1. When the BOOTRST fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Sup-port” on pa

ATmega163(L)21;$024 MAIN: ldi r16,high(RAMEND); Main program start$025 out SPH,r16 ; Set stack pointer to top of RAM$026 ldi r16,low(RAMEND)$027 out S

ATmega163(L)22Figure 24. Reset LogicNotes: 1. Values are guidelines only. Actual values are TBD.2. The Power-on Reset will not work unless the supply

ATmega163(L)23Notes: 1. On power-up, the start-up time is increased with typ. 0.6 ms.2. ‘1’ means unprogrammed, ‘0’ means programmed.3. For possible c

ATmega163(L)24Figure 25. MCU Start-up, RESET Tied to VCC.Figure 26. MCU Start-up, RESET Extended ExternallyExternal ResetAn external reset is genera

ATmega163(L)25Brown-out DetectionATmega163 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during the operation. The BOD

ATmega163(L)26MCU Status Register - MCUSRThe MCU Status Register provides information on which reset source caused an MCU reset.•Bits 7..4 - Res: Rese

ATmega163(L)27Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition ispresent.No

ATmega163(L)28•Bit 6 - INTF0: External Interrupt Flag0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-b

ATmega163(L)29The Timer/Counter Interrupt Flag Register - TIFR•Bit 7 - OCF2: Output Compare Flag 2The OCF2 bit is set (one) when a compare match occur

ATmega163(L)3DescriptionThe ATmega163 is a low-power CMOS 8-bit microcontroller based on the AVR architecture. By executing powerful instruc-tions in

ATmega163(L)30MCU Control Register - MCUCRThe MCU Control Register contains control bits for general MCU functions.•Bit 7 - Res: Reserved BitThis bit

ATmega163(L)31Sleep ModesTo enter any of the four sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed.The SM1

ATmega163(L)32When waking up from Power-down Mode, there is a delay from the wake-up condition occurs until the wake-up becomeseffective. This allows

ATmega163(L)33•Bit 3 - ACME: Analog Comparator Multiplexer EnableWhen this bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), the A

ATmega163(L)34sources. Setting the PSR10 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler.Note that Tim

ATmega163(L)35Figure 32. Timer/Counter0 Block DiagramTimer/Counter0 Control Register - TCCR0•Bits 7..3 - Res: Reserved BitsThese bits are reserved bi

ATmega163(L)36Timer/Counter 0 - TCNT0The Timer/Counter0 is implemented as an up-counter with read and write access. If the Timer/Counter0 is written a

ATmega163(L)37The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly,

ATmega163(L)38In PWM mode, these bits have a different function. Refer to Table 14 for a detailed description.•Bit 3 - FOC1A: Force Output Compare1AWr

ATmega163(L)39... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 |1,1,1,1,1,1,1,1|...In PWM mode, this bit

ATmega163(L)4The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directlyconnected to the

ATmega163(L)40The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1is written to and

ATmega163(L)41Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read toensure that both b

ATmega163(L)42Note: X = A or BNote that in the PWM mode, the 8, 9, or 10 least significant OCR1A/OCR1B bits (depending on resolution), when written,ar

ATmega163(L)43Figure 36. Effects of Unsynchronized OCR1 Latching in Overflow Mode.During the time between the write and the latch operation, a read f

ATmega163(L)448-Bit Timer/Counter 2Figure 37 shows the block diagram for Timer/Counter2.Figure 37. Timer/Counter2 Block DiagramThe 8-bit Timer/Counte

ATmega163(L)45Timer/Counter2 Control Register - TCCR2•Bit 7 - FOC2: Force Output CompareWriting a logical one to this bit, forces a change in the comp

ATmega163(L)46The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2clock.Timer/Counter2 -

ATmega163(L)47If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF.The PD7(OC2) pin wi

ATmega163(L)48Figure 39. Effects of Unsynchronized OCR Latching in Overflow Mode.During the time between the write and the latch operation, a read fr

ATmega163(L)49•Bit 2 - TCN2UB: Timer/Counter2 Update BusyWhen Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one).

ATmega163(L)5Port D (PD7..PD0)Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf

ATmega163(L)50• When the asynchronous operation is selected, the 32.768 kHZ oscillator for Timer/Counter2 is always running, except in power down mode

ATmega163(L)51Watchdog TimerThe Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1 Mhz. This is the typical value at VCC =5V

ATmega163(L)52•Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling

ATmega163(L)53EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time is in the range of 1.9 - 3.8 m

ATmega163(L)54•Bit 3 - EERIE: EEPROM Ready Interrupt EnableWhen the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When

ATmega163(L)551. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-

ATmega163(L)56Serial Peripheral Interface - SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega163

ATmega163(L)57Figure 42. SPI Master-slave InterconnectionThe system is single buffered in the transmit direction and double buffered in the receive d

ATmega163(L)58Data ModesThere are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bitsCPHA an

ATmega163(L)59•Bit 2 - CPHA: Clock PhaseRefer to Figure 43 and Figure 44 for the functionality of this bit.•Bits 1,0 - SPR1, SPR0: SPI Clock Rate Sele

ATmega163(L)6Crystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-

ATmega163(L)60UARTThe ATmega163 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver andTransmitter (UART)

ATmega163(L)61• A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loa

ATmega163(L)62samples 8, 9, and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noisespike and

ATmega163(L)631. All slave MCUs are in Multi-Processor Communication Mode (MPCM in UCSRA is set).2. The master MCU sends an address byte, and all slav

ATmega163(L)64The FE bit is cleared when the stop bit of received data is one.•Bit 3 - OR: OverRunThis bit is set if an Overrun condition is detected,

ATmega163(L)65Baud Rate GeneratorThe baud rate generator is a frequency divider which generates baud-rates according to the following equation:• BAUD

ATmega163(L)66UART Baud Rate Registers - UBRR and UBRRHIThis is a 12-bit register which contains the UART Baud Rate according to the equation on the p

ATmega163(L)67Table 28. UBR Settings at Various Crystal Frequencies in Double Speed Mode1.0000 MHz% Error1.8432 MHz% Error2.0000 MHz% ErrorUBR = 51 0

ATmega163(L)682-wire Serial Interface (Byte Oriented)The 2-wire Serial Interface supports bi-directional serial communication. It is designed primaril

ATmega163(L)69Figure 51. Block diagram of the 2-Wire Serial InterfaceThe CPU interfaces with the 2-wire Serial Interface via the following five I/O r

ATmega163(L)7Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cyc

ATmega163(L)70Note: Both the receiver and the transmitter can stretch the low period of the SCL line when waiting for user response, thereby reduc-ing

ATmega163(L)71The TWCR is used to control the operation of the 2-wire Serial Interface. It is used to enable the 2-wire Serial Interface, toinitiate a

ATmega163(L)72ator that looks for the slave address (or generall call address if enabled) in the received serial address. If a match is found,an inter

ATmega163(L)73TWCR register. This scheme is repeated until the last byte is sent and the transfer is ended by generating a STOP condi-tion or a repeat

ATmega163(L)74address by using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the 2-wire SerialInterface wil

ATmega163(L)75Table 32. Status Codes for Master Transmitter ModeStatus code(TWSR)Status of the 2-wire Serial Bus and 2-wire Serial Interface hardware

ATmega163(L)76Figure 52. Formats and States in the Master Transmitter ModeAssembly Code Example - Master Transmitter Mode;The slave being addressed h

ATmega163(L)77rjmp wait1in r16, TWSR ; Check value of TWI Status Register.cpi r16, START ; If status different from START go to ERRORbrne ERRORldi r16

ATmega163(L)78Table 33. Status Ccodes for Master Receiver ModeStatus code(TWSR)Status of the 2-wire Serial Bus and 2-wire Serial Interface hardwareAp

ATmega163(L)79Figure 53. Formats and States in the Master Receiver ModeAssembly Code Example - Master Receiver Mode;Part specific include file and TW

ATmega163(L)8The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The programmemory is executed with a

ATmega163(L)80wait6: in r16,TWCR ; Wait for TWINT flag set. This indicates thatsbrs r16, TWINT ; SLA+R has been transmitted, and ACK/NACK hasrjmp wait

ATmega163(L)81brne ERRORin r16, TWDR ; Input received data from TWDR.nop ;<do something with received data>ldi r16, (1<<TWINT) | (1<<

ATmega163(L)82Figure 54. Formats and States in the Slave Receiver Mode$A0 A STOP condition or repeated START condition has been received while still

ATmega163(L)83Assembly Code Example - Slave Receiver Mode;Part specific include file and TWI include file must be included.; <Initialize registers

ATmega163(L)84in r16, TWSR ; Check value of TWI Status Register. If statuscpi r16, SR_DATA_NACK ; different from SR_DATA_NACK, go to ERRORbrne ERRORin

ATmega163(L)85Figure 55. Formats and States in the Slave Transmitter ModeAssembly Code Example - Slave Transmitter Mode; Part specific include file a

ATmega163(L)86in r16, TWSR ; Check value of TWI Status Register. If statuscpi r16, ST_DATA_ACK ; different from ST_DATA_ACK, go to ERRORbrne ERRORldi

ATmega163(L)87TWI Include File;***** General Master staus codes *****.equ START =$08 ;START has been transmitted.equ REP_START =$10 ;Repeated START ha

ATmega163(L)88The Analog ComparatorThe analog comparator compares the input values on the positive pin PB2 (AIN0) and negative pin PB3 (AIN1). When th

ATmega163(L)89•Bit 3 - ACIE: Analog Comparator Interrupt EnableWhen the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the a

ATmega163(L)9The General Purpose Register FileFigure 7 shows the structure of the 32 general purpose working registers in the CPU.Figure 7. AVR CPU G

ATmega163(L)90Analog to Digital ConverterFeature List:•10-bit Resolution• 0.5 LSB Integral Non-linearity• ±2 LSB Absolute Accuracy• 65 - 260 µs Conver

ATmega163(L)91Figure 57. Analog to Digital Converter Block SchematicOperationThe ADC converts an analog input voltage to a 10-bit digital value throu

ATmega163(L)92The ADC can operate in two modes - Single Conversion and Free Running Mode. In Single Conversion Mode, each con-version will have to be

ATmega163(L)93switched on (ADEN in ADCSR is set). Additionally, when changing voltage reference, the user may improve accuracy bydisregarding the firs

ATmega163(L)94Figure 61. ADC Timing Diagram, Free Run ConversionADC Noise Canceler FunctionThe ADC features a noise canceler that enables conversion

ATmega163(L)95The ADC Multiplexer Selection Register - ADMUX•Bit 7,6 - REFS1..0: Reference Selection BitsThese bits select the voltage reference for t

ATmega163(L)96The ADC Control and Status Register - ADCSR•Bit 7 - ADEN: ADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this

ATmega163(L)97The ADC Data Register - ADCL and ADCHADLAR = 0:ADLAR = 1:When an ADC conversion is complete, the result is found in these two registers.

ATmega163(L)98Figure 62. ADC Power ConnectionsNotes: 1. Values are guidelines only. Actual values are TBD.2. Minimum for AVCC is 2.7V.3. Maximum for

ATmega163(L)99I/O-PortsAll AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direc-tion