Rainbow-electronics ATmega163L Manuel d'utilisateur télécharger pdf (Page 42)

ATmega163(L)

Note: X = A or B

Note that in the PWM mode, the 8, 9, or 10 least significant OCR1A/OCR1B bits (depending on resolution), when written,

are transferred to a temporary location. They are latched when Timer/Counter1 reaches the value TOP. This prevents the

occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 35

and Figure 36 for an example in each mode.

Figure 35. Effects of Unsynchronized OCR1 Latching.

Table 17. Compare1 Mode Select in PWM Mode

CTC1 COM1X

COM1X

Effect on OCX1

0 0 0 Not connected

0 0 1 Not connected

0 1 0 Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM).

0 1 1 Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM).

1 0 0 Not connected

1 0 1 Not connected

1 1 0 Cleared on compare match, set on overflow.

1 1 1 Set on compare match, cleared on overflow.

PWM Output OC1x

Unsynchronized OC1x Latch

Synchronized OC1x Latch

Note: x = A or B

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 155 156

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Rainbow-electronics ATmega163L Manuel d'utilisateur Page 42