Rainbow-electronics ATmega64L Manuel d'utilisateur télécharger pdf (Page 103)

103

ATmega16(L)

2466B–09/01

Figure 51 shows the count sequence close to TOP in various modes. When using phase

and frequency correct PWM mode the OCR1x register is updated at BOTTOM. The tim-

ing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by

BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at

BOTTOM.

Figure 51. Timer/Counter Timing Diagram, no Prescaling

Figure 52 shows the same timing data, but with the prescaler enabled.

Figure 52. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O

/8)

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

(clk

I/O

/1)

clk

I/O

TOVn (FPWM)

and ICFn (if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

1 2 ... 98 99 100 101 102 103 104 105 106 107 108 ... 297 298

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Rainbow-electronics ATmega64L Manuel d'utilisateur Page 103

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