Rainbow-electronics ATmega64L Manuel d'utilisateur télécharger pdf (Page 234)

100

101

234

ATmega16(L)

2466B–09/01

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock

frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency

has to be at least five times the number of scan bits divided by the maximum hold time,

hold,max

9 1 0x143 0x08 1 1 0 0 0

10 1 0x143 0x08 1 0 0 0 0

11 Verify the

COMP bit

scanned

out to be

1 0x200 0x08 1 1 0 0 0

Table 93. Algorithm for Using the ADC (Continued)

Step Actions ADCEN DAC MUXEN HOLD PRECH

PA3.

Data

PA3.

Control

PA3.

Pullup_

Enable

1 2 ... 229 230 231 232 233 234 235 236 237 238 239 ... 297 298

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Rainbow-electronics ATmega64L Manuel d'utilisateur Page 234

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