Rainbow-electronics ATmega64M1 Manuel d'utilisateur Page 153

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153
8209A–AVR–08/09
ATmega16M1/32M1/64M1
Bit 2 – PEVE1: PSC External Event 1 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 1 generates also
an interrupt.
Bit 1 – PEVE : PSC External Event 0 Interrupt Enable
When this bit is set, an external event which can generates a fault on module 0 generates also
an interrupt.
Bit 0 – PEOPE: PSC End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
18.16.11 PIFR – PSC Interrupt Flag Register
Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
Bit 3 – PEV2: PSC External Event 2 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 2
occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE2 bit = 0).
Bit 2 – PEV1: PSC External Event 1 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 1
occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE1 bit = 0).
Bit 1 – PEV : PSC External Event 0 Interrupt
This bit is set by hardware when an external event which can generates a fault on module 0
occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVE0 bit = 0).
Bit 0 – PEOP: PSC End Of Cycle Interrupt
This bit is set by hardware when an “end of PSC cycle” occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEOPE bit = 0).
Bit 76543210
- - - - PEV2 PEV1 PEV0 PEOP PIFR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
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