Figure 22-18. Amplifiers block diagram
AMP0TS1 AMP0TS0AMP0EN AMP0IS AMP0G1 AMP0G0
AMP0CSR
+
-
SAMPLING
AMP0+
AMP0-
Toward ADC MUX
(AMP0)
Amplifier 0
Clock
01
10
01
00
AMPCMP0 AMP0TS2
AMP1TS1 AMP1TS0
AMP1EN AMP1IS AMP1G1 AMP1G0
AMP1CSR
+
-
SAMPLING
AMP1+
AMP1-
Toward ADC MU
(AMP1)
Amplifier 1
Clock
01
10
01
00
AMPCMP1 AMP1TS2
AMP2TS1 AMP2TS0
AMP2EN AMP2IS AMP2G1 AMP2G0
AMP2CSR
+
-
SAMPLING
AMP2+
AMP2-
Toward ADC MU
(AMP2)
Amplifier 2
Clock
ADCK/8
PSS0
PSS1
PSS2
AMPCMP2 AMP2TS2
Timer 0 Compare Match
Timer 0 Overflow
Timer 1 Compare Match
Timer 1 Overflow
ADCK/8
PSS0
PSS1
PSS2
Timer 0 Compare Match
Timer 0 Overflow
Timer 1 Compare Match
Timer 1 Overflow
ADCK/8
PSS0
PSS1
PSS2
Timer 0 Compare Match
Timer 0 Overflow
Timer 1 Compare Match
Timer 1 Overflow
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