
32
8052B–AVR–09/08
ATmega4HVD/8HVD
9. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
9.1 Sleep Modes
Figure 8-1 on page 22 presents the different clock systems in the ATmega4HVD/8HVD, and
their distribution. The figure is helpful in selecting an appropriate sleep mode. The different
sleep modes and their wake-up sources are summarized in Table 9-1, and Figure 9-1 on page
33 shows a sleep mode state diagram.
Note: 1. Discharge FET must be switched off for Charger Detect to be active.
To enter any of the available sleep modes, the SE bit in SMCR must be written to logic one
and a SLEEP instruction must be executed. The SM2:0 bits in the SMCR Register select
which sleep mode (Idle, ADC NRM, Power-save or Power-off) will be activated by the SLEEP
instruction. See Table 9-3 on page 36 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the register file and
SRAM are unaltered when the device wakes up from any sleep mode. If a reset occurs during
sleep mode, the MCU wakes up and executes from the Reset Vector.
Table 9-1. Wake-up Sources for Sleep Modes
Mode
Wake-up sources
Battery Protection
Interrupts
External Interrupts
WDT
EEPROM Ready
VREGMON
ADC
Other I/O
Charger Detect
(1)
Idle
X XXXXXX
ADC Noise Reduction
X XXXXX
Power-save
XXX
Power-off
X
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