Rainbow-electronics ATmega8HVD Manuel d'utilisateur télécharger pdf (Page 87)

8052B–AVR–09/08

ATmega4HVD/8HVD

16.10.2 TCNTnL – Timer/Counter n Register Low Byte

The Timer/Counter Register TCNTnL gives direct access, both for read and write operations,

to the Timer/Counter unit 8-bit counter. Writing to the TCNTnL Register blocks (disables) the

Compare Match on the following timer clock. Modifying the counter (TCNTnL) while the coun-

ter is running, introduces a risk of missing a Compare Match between TCNTnL and the

OCRnx Registers. In 16-bit mode the TCNTnL register contains the lower part of the 16-bit

Timer/Counter n Register.

16.10.3 TCNTnH – Timer/Counter n Register High Byte

When 16-bit mode is selected (the TCWn bit is set to one) the Timer/Counter Register

TCNTnH combined to the Timer/Counter Register TCNTnL gives direct access, both for read

and write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high

and low bytes are read and written simultaneously when the CPU accesses these registers,

the access is performed using an 8-bit temporary high byte register (TEMP). This temporary

page 82.

16.10.4 OCRnA – Timer/Counter n Output Compare Register A

The Output Compare Register A contains an 8-bit value that is continuously compared with

the counter value (TCNTnL). A match can be used to generate an Output Compare interrupt.

In 16-bit mode the OCRnA register contains the low byte of the 16-bit Output Compare Regis-

ter. To ensure that both the high and the low bytes are written simultaneously when the CPU

writes to these registers, the access is performed using an 8-bit temporary high byte register

(TEMP). This temporary register is shared by all the other 16-bit registers. See ”Accessing

Registers in 16-bit Mode” on page 82.

16.10.5 OCRnB – Timer/Counter n Output Compare Register B

The Output Compare Register B contains an 8-bit value that is continuously compared with

the counter value (TCNTnL in 8-bit mode and TCNTnH in 16-bit mode). A match can be used

to generate an Output Compare interrupt.

Bit 76543210

TCNTnL[7:0] TCNTnL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

TCNTnH[7:0] TCNTnH

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCRnA[7:0] OCRnA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

OCRnB[7:0] OCRnB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 167 168

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