Rainbow-electronics ATmega128L Manuel d'utilisateur télécharger pdf (Page 126)

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101

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ATmega128(L)

2467B–09/01

Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f

clk_I/O

/8)

Figure 56 shows the count sequence close to TOP in various modes. When using phase

and frequency correct PWM mode the OCRnx register is updated at BOTTOM. The tim-

ing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by

BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at

BOTTOM.

Figure 56. Timer/Counter Timing Diagram, no Prescaling

Figure 57 shows the same timing data, but with the prescaler enabled.

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(clk

I/O

/8)

TOVn

(FPWM)

and ICFn

(if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

(clk

I/O

/1)

clk

I/O

1 2 ... 121 122 123 124 125 126 127 128 129 130 131 ... 330 331

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Rainbow-electronics ATmega128L Manuel d'utilisateur Page 126

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