Rainbow-electronics ATmega128L Manuel d'utilisateur télécharger pdf (Page 162)

162

ATmega128(L)

2467B–09/01

• Bit 3 - CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero,

SCK is low when idle. Refer to Figure 76 and Figure 77 for an example. The CPOL func-

tionality is summarized below:

• Bit 2 - CPHA: Clock Phase

The settings of the clock phase bit (CPHA) determine if data is sampled on the leading

(first) or trailing (last) edge of SCK. Refer to

Figure 76 and Figure 77 for an example.

The CPOL functionality is summarized below:

• Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a master. SPR1 and

SPR0 have no effect on the slave. The relationship between SCK and the Oscillator

Clock frequency f

osc

is shown in the following table:

SPI Status Register – SPSR

• Bit 7 - SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE

in SPCR is set and global interrupts are enabled. If SS

is an input and is driven low

when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, the

Table 70. CPOL functionality

CPOL Leading edge Trailing edge

0 Rising Falling

1 Falling Rising

Table 71. CPHA functionality

CPHA Leading edge Trailing edge

0 Sample Setup

1Setup Sample

Table 72. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000

osc

001

osc

/16

010

osc

/64

011

osc

/128

100

osc

101

osc

110

osc

/32

111

osc

/64

Bit 76543210

SPIF WCOL –––––SPI2X SPSR

Read/WriteRRRRRRRR/W

Initial value00000000

1 2 ... 157 158 159 160 161 162 163 164 165 166 167 ... 330 331

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Rainbow-electronics ATmega128L Manuel d'utilisateur Page 162

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