Rainbow-electronics ATmega128L Manuel d'utilisateur télécharger pdf (Page 314)

314

ATmega128(L)

2467B–09/01

5. This requirement applies to all ATmega128 2-wire Serial Interface operation. Other

devices connected to the 2-wire Serial Bus need only obey the general f

SCL

requirement.

6. The actual low period generated by the ATmega128 2-wire Serial Interface is (1/f

SCL

2/f

), thus f

must be greater than 6 MHz for the low time requirement to be strictly

met at f

SCL

= 100 kHz.

7. The actual low period generated by the ATmega128 2-wire Serial Interface is (1/f

SCL

2/f

), thus the low time requirement will not be strictly met for f

SCL

> 308 kHz when

= 8 MHz. Still, ATmega128 devices connected to the bus may communicate at full

speed (400 kHz) with other ATmega128 devices, as well as any other device with a

proper t

LOW

acceptance margin.

Figure 153. 2-wire Serial Bus Timing

SPI Timing

Characteristics

See Figure 154 and Figure 155 for details.

SU;STA

LOW

HIGH

LOW

HD;STA

HD;DAT

SU;DAT

SU;STO

BUF

SCL

SDA

Table 136. SPI Timing Parameters

Description Mode Min Typ Max

1 SCK period Master See Table 72

2 SCK high/low Master 50% duty cycle

3 Rise/Fall time Master TBD

4 Setup Master TBD

5HoldMaster TBD

6 Out to SCK Master TBD

7 SCK to out Master TBD

8 SCK to out high Master TBD

9 SS low to out Slave TBD

10 SCK period Slave 4 • t

TBD

11 SCK high/low Slave 2 • t

TBD

12 Rise/Fall time Slave TBD

13 Setup Slave TBD

14 Hold Slave TBD

15 SCK to out Slave TBD

16 SCK to SS

high Slave TBD

17 SS

high to tri-state Slave TBD

1 2 ... 309 310 311 312 313 314 315 316 317 318 319 ... 330 331

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