Rainbow-electronics ATmega128L Manuel d'utilisateur télécharger pdf (Page 321)

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101

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ATmega128(L)

2467B–09/01

Figure 158. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

Figure 159. External Memory Timing (SRWn1 = 1, SRWn0 = 1)

(1)

Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction

accesses the RAM (internal or external).

ALE

T1 T2 T3

Write

Read

A15:8

Address

Prev. addr.

DA7:0

Address DataPrev. data XX

DA7:0 (XMBK = 0)

Data

Prev. data Address

System Clock (CLK

CPU

)

8 12

ALE