124
ATmega8515(L)
2512A–AVR–04/02
When configured as a Master, the SPI interface has no automaticcontrol of the SS line.
This must be handledbyusersoftware before communication can start. When this is
done,writing a byte to the SPIData Registerstarts the SPIclock generator, and the
hardware shifts the8bits into the Slave. Aftershifting one byte, the SPIclock generator
stops, setting theend of transmission flag (SPIF). If the SPIInterrupt Enable bit (SPIE)
in the SPCR Register isset, an interruptisrequested.The Master maycontinue to shift
thenext byte by writing it into SPDR, orsignal theend ofpacket by pulling high the
Slave Select,SS
line. The lastincoming byte will be keptinthe bufferregisterforlater
use.
When configured as a Slave, the SPI interface will remain sleeping withMISOtri-stated
aslong as the SS
pin isdriven high. Inthisstate,softwaremay update the contents of
the SPIData Register, SPDR,but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS
pin isdriven low.As one byte hasbeen completely
shifted, theend of transmission flag,SPIF isset. If the SPIInterrupt Enable bit,SPIE, in
the SPCRRegister isset, an interruptisrequested.The Slave maycontinue to place
newdata to be sent into SPDR before reading theincoming data. The lastincoming byte
will be keptinthe bufferregisterforlater use.
Figure 60. SPIMaster-slave Interconnection
The system issingle buffered in thetransmit direction anddouble buffered in the receive
direction. This means that bytes to betransmittedcannot be writtentothe SPIData
Registerbeforethe entire shift cycleiscompleted. When receiving data,however, a
receivedcharacter must be readfrom the SPIData Registerbeforethenext character
hasbeen completely shifted in. Otherwise, the first byte islost.
In SPISlave mode, the controllogicwill sampletheincoming signal of the SCK pin. To
ensure correct sampling of the clock signal, the frequency of the SPIclock should never
exceedf
osc
/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, andSS
pins is
overridden according to Table55.For more details on automaticportoverrides, refer to
“Alternate Port Functions”onpage 61.
Note: 1. See “Alternate FunctionsOfPort B”onpage 64 for a detaileddescription ofhow to
define the direction of theuserdefinedSPIpins.
Table 55. SPI Pin Overrides
(1)
Pin Direction, Master SPI Direction, Slave SPI
MOSI UserDefinedInput
MISO Input UserDefined
SCK UserDefinedInput
SS
UserDefinedInput
MSB MASTER LSB
8-BIT SHIFT REGISTER
MSB SLAVE LSB
8-BIT SHIFT REGISTER
MISO
MOSI
SPI
CLOCK GENERATOR
SCK
SS
MISO
MOSI
SCK
SS
V
CC
SHIFT
ENABLE
(24 pages)
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