Rainbow-electronics ATmega8515L Manuel d'utilisateur télécharger pdf (Page 85)

ATmega8515(L)

2512A–AVR–04/02

Phase Correct PWM Mode The phase correctPWM mode (WGM01:0 =3)provides a highresolution phase correct

PWM waveform generation option. The phase correctPWM modeisbased on a dual-

slopeoperation. The countercountsrepeatedly from BOTTOM to MAX and then from

MAX to BOTTOM. Innon-inverting Compare Output mode, the Output Compare (OC0)

iscleared on the comparematch between TCNT0 andOCR0 whileupcounting, andset

on the comparematch while downcounting. Ininverting Output Comparemode, the

operation is inverted.The dual-slopeoperation haslower maximum operation frequency

than single slopeoperation. However, due to the symmetricfeatureof the dual-slope

PWM modes, thesemodes are preferredfor motorcontrol applications.

ThePWM resolution for the phase correctPWM modeisfixed to eight bits. In phase

correctPWM modethe counter is incremented until the counter value matchesMAX.

When the counterreachesMAX, it changes the count direction. TheTCNT0 value will

beequal to MAXfor one timerclock cycle. The timing diagram for the phase correct

PWM modeisshownonFigure 39.TheTCNT0 value is in the timing diagram shownas

a histogram for illustrating the dual-slopeoperation. The diagram includes non-inverted

and inverted PWM outputs.The small horizontalline marks on theTCNT0 slopesrepre-

sent comparematchesbetween OCR0 and TCNT0.

Figure 39. Phase CorrectPWM Mode, Timing Diagram

TheTimer/CounterOverflowFlag (TOV0) isset each time the counterreachesBOT-

TOM.Theinterrupt flag can beused to generate an interrupteach time the counter

reaches the BOTTOM value.

In phase correctPWM mode, the compareunitallows generation of PWM waveforms on

the OC0 pin. Setting the COM01:0 bits to 2 will produceanon-inverted PWM.An

inverted PWM output can begeneratedbysetting the COM01:0to3(See Table47 on

page 89).TheactualOC0value will only bevisibleonthe port pin if the data direction

for the port pin isset as output. ThePWM waveformis generatedbyclearing (orsetting)

the OC0Register at the comparematch between OCR0 and TCNT0 when the counter

increments, andsetting (orclearing) the OC0 Register at comparematch between

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 222 223

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Rainbow-electronics ATmega8515L Manuel d'utilisateur Page 85