
64
ATmega8515(L)
2512A–AVR–04/02
Alternate Functions Of Port B ThePort Bpinswith alternate functions are showninTable29.
Thealternate pin configuration is asfollows:
•SCK–PortB,Bit7
SCK: MasterClock output,Slave Clock input pin forSPIchannel. When the SPI is
enabled as a Slave, thispin isconfigured as an input regardless of the setting of DDB7.
When the SPI is enabled as a Master, the data direction of thispin iscontrolledby
DDB7. When the pin isforcedbythe SPI to beaninput, the pull-upcan still be con-
trolledbythePORTB7 bit.
• MISO – Port B, Bit 6
MISO: MasterData input,Slave Data output pin forSPIchannel. When the SPI is
enabled as a Master, thispin isconfigured as an input regardless of the setting of
DDB6. When the SPI is enabled as a Slave, the data direction of thispin iscontrolledby
Table 28. Overriding Signals for Alternate Functions in PA3..PA0
Signal
Name PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0
PUOE SRESRESRESRE
PUOV ~(WR
| ADA) •
PortA3
~(WR | ADA) •
PortA2
~(WR
| ADA) •
PortA1
~(WR
| ADA) •
PortA0
DDOE SRESRESRESRE
DDOV WR
| ADA WR | ADA WR | ADA WR | ADA
PVOE SRESRESRESRE
PVOVA3 •ADA |
D3 OUTPUT•
WR
A2 • ADA |
D2 OUTPUT•
WR
A1 • ADA |
D1 OUTPUT•
WR
A0 • ADA |
D0 OUTPUT•
WR
DIEOE 0000
DIEOV0 0 0 0
DI D3 INPUT D2 INPUT D1 INPUT D0 INPUT
AIO ––––
Table 29. Port B Pins Alternate Functions
Port Pin Alternate Functions
PB7 SCK (SPIBusSerialClock)
PB6 MISO (SPIBusMasterInput/Slave Output)
PB5 MOSI (SPIBusMasterOutput/Slave Input)
PB4 SS
(SPISlave Select Input)
PB3 AIN1 (Analog ComparatorNegative Input)
PB2AIN0 (Analog Comparator Positive Input)
PB1T1(Timer/Counter1 ExternalCounterInput)
PB0
T0 (Timer/Counter0 ExternalCounterInput)
OC0 (Timer/Counter0 Output Compare Match Output)
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