Rainbow-electronics ATmega8515L Manuel d'utilisateur télécharger pdf (Page 199)

199

ATmega8515(L)

2512A–AVR–04/02

External Data Memory Timing

Notes: 1. This assumes 50%clock duty cycle. The half period is actually the high time of theexternalclock, XTA L1.

2. This assumes 50%clock duty cycle. The half period is actually the low time of theexternalclock, XTA L1.

Table 99. ExternalData Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL

OscillatorFrequency 0.0 16MHz

LHLL

ALE Pulse Width 115 1.0t

CLCL

-10 ns

AVLL

Address Valid AtoALE Low 57.5 0.5t

CLCL

-5

(1)

3at

LLAX_ST

Address Hold After ALE Low,

write access

3b t

LLAX_LD

Address Hold after ALE Low,

read access

AVLLC

Address ValidCto ALE Low 57.5 0.5t

CLCL

-5

(1)

AVRL

Address Valid to RDLow 115 1.0t

CLCL

-10 ns

6 t

AVWL

Address Valid to WR Low 115 1.0t

CLCL

-10 ns

7 t

LLWL

ALE Low to WR Low 47.5 67.5 0.5t

CLCL

-15

(2)

0.5t

CLCL

(2)

LLRL

ALE Low to RDLow 47.5 67.5 0.5t

CLCL

-15

(2)

0.5t

CLCL

(2)

9 t

DVRH

Data Setup to RDHigh 40 40 ns

10 t

RLDV

ReadLow to Data Valid751.0t

CLCL

-50 ns

11 t

RHDX

Data Hold After RDHigh 00 ns

12 t

RLRH

RD Pulse Width 115 1.0t

CLCL

-10 ns

13 t

DVWL

Data Setup to WR Low 42.5 0.5t

CLCL

-20

(1)

14 t

WHDX

Data Hold AfterWR High 115 1.0t

CLCL

-10 ns

15 t

DVWH

Data Valid to WR High 125 1.0t

CLCL

16 t

WLWH

WRPulse Width 115 1.0t

CLCL

-10 ns

Table 100. ExternalData Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL

OscillatorFrequency 0.0 16MHz

10 t

RLDV

ReadLow to Data Valid 200 2.0t

CLCL

-50 ns

12 t

RLRH

RD Pulse Width 240 2.0t

CLCL

-10 ns

15 t

DVWH

Data Valid to WR High 240 2.0t

CLCL

16 t

WLWH

WRPulse Width 240 2.0t

CLCL

-10 ns

1 2 ... 194 195 196 197 198 199 200 201 202 203 204 ... 222 223

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