Rainbow-electronics Atmega169L Manuel d'utilisateur télécharger pdf (Page 244)

244

ATmega169V/L

2514A–AVR–08/02

As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3

when the power supply is 5.0V and AREF is externally connected to V

The recommended values from Table 105 are used unless other values are given in the

algorithm in Table 106. Only the DAC and port pin values of the Scan Chain are shown.

The column “Actions” describes what JTAG instruction to be used before filling the

Boundary-scan Register with the succeeding columns. The verification should be done

on the data scanned out when scanning in the data on the same row in the table.

Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock

frequency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency

has to be at least five times the number of scan bits divided by the maximum hold time,

hold,max

Table 106. Algorithm for Using the ADC

Step Actions ADCEN DAC MUXEN HOLD PRECH

PA3.

Data

PA3.

Control

PA3.

Pullup_

Enable

SAMPLE_

PRELOAD

1 0x200 0x08 1 1 0 0 0

2 EXTEST

1 0x200 0x08 0 1 0 0 0

1 0x200 0x08 1 1 0 0 0

1 0x123 0x08 1 1 0 0 0

5 1 0x123 0x08 1 0 0 0 0

Verify the

COMP bit

scanned

outtobe0

1 0x200 0x08 1 1 0 0 0

1 0x200 0x08 0 1 0 0 0

1 0x200 0x08 1 1 0 0 0

1 0x143 0x08 1 1 0 0 0

1 0x143 0x08 1 0 0 0 0

Verify the

COMP bit

scanned

outtobe1

1 0x200 0x08 1 1 0 0 0

The lower limit is: 1024 1.5V 0,95 5V⁄⋅⋅ 291 0x123==

The upper limit is: 1024 1.5V 1.05 5V⁄⋅⋅ 323 0x143==

1 2 ... 239 240 241 242 243 244 245 246 247 248 249 ... 316 317

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Rainbow-electronics Atmega169L Manuel d'utilisateur Page 244

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