Rainbow-electronics Atmega169L Manuel d'utilisateur télécharger pdf (Page 278)

278

ATmega169V/L

2514A–AVR–08/02

Figure 126. Parallel Programming Timing, Reading Sequence (within the Same Page)

with Timing Requirements

(1)

Note: 1. The timing requirements shown in Figure 124 (i.e., t

DVXH

XHXL

, and t

XLDX

) also apply

to reading operation.

Table 128. Parallel Programming Characteristics, V

=5V±10%

Symbol Parameter Min Typ Max Units

Programming Enable Voltage 11.5 12.5 V

Programming Enable Current 250 µA

DVXH

Data and Control Valid before XTAL1 High 67 ns

XLXH

XTAL1 Low to XTAL1 High 200 ns

XHXL

XTAL1 Pulse Width High 150 ns

XLDX

Data and Control Hold after XTAL1 Low 67 ns

XLWL

XTAL1 Low to WR Low 0 ns

XLPH

XTAL1 Low to PAGEL high 0 ns

PLXH

PAGEL low to XTAL1 high 150 ns

BVPH

BS1 Valid before PAGEL High 67 ns

PHPL

PAGEL Pulse Width High 150 ns

PLBX

BS1 Hold after PAGEL Low 67 ns

WLBX

BS2/1 Hold after WR Low 67 ns

PLWL

PAG E L L ow to W R Low 67 ns

BVWL

BS1 Valid to WR Low 67 ns

WLWH

WR Pulse Width Low 150 ns

WLRL

WR Low to RDY/BSY Low 0 1 µs

WLRH

WR Low to RDY/BSY High

(1)

3.7 4.5 ms

WLRH_CE

WR Low to RDY/BSY High for Chip Erase

(2)

7.5 9 ms

XLOL

XTAL1 Low to OE Low 0 ns

XTAL1

ADDR0 (Low Byte) DATA (Low Byte)

DATA (High Byte)

ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE)

READ DATA

(LOW BYTE)

READ DATA

(HIGH BYTE)

LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

1 2 ... 273 274 275 276 277 278 279 280 281 282 283 ... 316 317

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