Rainbow-electronics Atmega169L Manuel d'utilisateur Page 95

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95
ATmega169V/L
2514AAVR08/02
Figure 39. 16-bit Timer/Counter Block Diagram
(1)
Note: 1. Refer to Figure 1 on page 2, Table 28 on page 58, and Table 34 on page 62 for
Timer/Counter1 pin placement and description.
Registers The
Timer/Counter
(TCNT1),
Output Compare Registers
(OCR1A/B), and
Input Capture
Register
(ICR1) are all 16-bit registers. Special procedures must be followed when
accessing the 16-bit registers. These procedures are described in the section Access-
ing 16-bit Registerson page 97. The
Timer/Counter Control Registers
(TCCR1A/B) are
8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to
Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register
(TIFR1).
All interrupts are individually masked with the
Timer Interrupt Mask Register
(TIMSK1).
TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the T1 pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
T
1
).
The double buffered Output Compare Registers (OCR1A/B) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform
Generator to generate a PWM or variable frequency output on the Output Compare pin
(OC1A/B). See Output Compare Units on page 103.. The compare match event will
Clock Select
Timer/Counter
DATA B U S
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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