Rainbow-electronics ATmega64C1 Manuel d'utilisateur télécharger pdf (Page 249)

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101

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7647A–AVR–02/08

ATmega32/64/M1/C1

Figure 18-17. Amplifier synchronization timing diagram

ADSC is set when the amplifier output is changing due to the amplifier clock

switch

In order to have a better understanding of the functioning of the amplifier synchronization, a tim-

ing diagram example is shown Figure 18-15.

It is also possible to auto trigger conversion on the amplified channel. In this case, the conver-

sion is started at the next amplifier clock event following the last auto trigger event selected

thanks to the ADTS bits in the ADCSRB register. In auto trigger conversion, the free running

mode is not possible unless the ADSC bit in ADCSRA is set by soft after each conversion.

The block diagram of the two amplifiers is shown on Figure 18-18.

Valid sample

Signal to be

measured

AMPLI_clk

(Sync Clock)

CK ADC

PSCn_ASY

PSC

Block

ADSC

ADC

Activity

ADC

Sampling

ADC

Co n v

ADC

Sampling

ADC

Co n v

ADC

Sampling

Aborted

ADC Result

Ready

ADC Result

Ready

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Rainbow-electronics ATmega64C1 Manuel d'utilisateur Page 249

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