Rainbow-electronics ATmega64C1 Manuel d'utilisateur télécharger pdf (Page 30)

7647A–AVR–02/08

ATmega32/64/M1/C1

5.1.4 PLL Clock – clk

PLL

The PLL clock allows the fast peripherals to be clocked directly from a 64/32 MHz clock. A 16

MHz clock is also derived for the CPU.

5.1.5 ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

5.2 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as illustrated

Table 5-1. The clock from the selected source is input to the AVR clock generator, and routed to

the appropriate modules.

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

2. Ext Osc : External Osc

3. RC Osc : Internal RC Oscillator

4. Ext Clk : External Clock Input

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before starting

normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up

time. The number of WDT Oscillator cycles used for each time-out is shown in Table 5-2. The

Table 5-1. Device Clocking Options Select

(1)

Device Clocking Option System

Clock PLL Input

CKSEL3..0

External Crystal/Ceramic Resonator Ext Osc RC Osc 1111 - 1000

PLL output divided by 4 : 16 MHz / PLL driven by External

Crystal/Ceramic Resonator

Ext Osc Ext Osc 0100

PLL output divided by 4 : 16 MHz / PLL driven by External

Crystal/Ceramic Resonator

PLL / 4 Ext Osc 0101

Reserved N/A N/A 0110

Reserved N/A N/A 0111

PLL output divided by 4 : 16 MHz PLL / 4 RC Osc 0011

Calibrated Internal RC Oscillator RC Osc RC Osc 0010

PLL output divided by 4 : 16 MHz / PLL driven by External

clock

PLL / 4 Ext Clk 0001

External Clock Ext Clk RC Osc 0000

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 365 366

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Rainbow-electronics ATmega64C1 Manuel d'utilisateur Page 30

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