Rainbow-electronics ATmega64C1 Manuel d'utilisateur télécharger pdf (Page 314)

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314

7647A–AVR–02/08

ATmega32/64/M1/C1

25.7 SPI Timing Characteristics

See Figure 25-3 and Figure 25-4 for details.

Note: In SPI Programming mode the minimum SCK high/low period is:

- 2 t

CLCL

for f

< 12 MHz

- 3 t

CLCL

for f

>12 MHz

Figure 25-3. SPI Interface Timing Requirements (Master Mode)

Table 4. SPI Timing Parameters

Description Mode Min. Typ. Max.

1 SCK period Master See Table 15-4

2 SCK high/low Master 50% duty cycle

3 Rise/Fall time Master 3.6

4 Setup Master 10

5 Hold Master 10

6 Out to SCK Master 0.5 • t

sck

7 SCK to out Master 10

8 SCK to out high Master 10

9 SS low to out Slave 15

10 SCK period Slave 4 • t

11 SCK high/low

(1)

Slave 2 • t

12 Rise/Fall time Slave 1600

13 Setup Slave 10

14 Hold Slave t

15 SCK to out Slave 15

16 SCK to SS

high Slave 20

17 SS high to tri-state Slave 10

18 SS low to SCK Slave 20

MOSI

(Data Output)

SCK

(CPOL = 1)

MISO

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

345

1 2 ... 309 310 311 312 313 314 315 316 317 318 319 ... 365 366

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